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author | Freddie Liardet <frederick.liardet@arm.com> | 2021-09-03 15:08:23 +0100 |
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committer | Freddie Liardet <frederick.liardet@arm.com> | 2021-10-12 15:41:04 +0000 |
commit | ded3663274db0e4359461659fb3c813792df16e3 (patch) | |
tree | d2a6146ef4affca9a90ae1508202ec3a25f6a2f6 /src/cpu/operators | |
parent | 0d11b70fbfa95431dacd7dce02403cf90bc688d5 (diff) | |
download | ComputeLibrary-ded3663274db0e4359461659fb3c813792df16e3.tar.gz |
Remove padding in cpuPool2d NCHW
Remove padding from all cpuPool2d NCHW kernels (FP16,FP32 & Quantized)
Resolves: COMPMID-4728, COMPMID-4823
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: Ida619f67cd6606b33828f2d9dee925aeb794cc50
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6358
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/operators')
-rw-r--r-- | src/cpu/operators/CpuPool2d.cpp | 28 | ||||
-rw-r--r-- | src/cpu/operators/CpuPool2d.h | 1 |
2 files changed, 0 insertions, 29 deletions
diff --git a/src/cpu/operators/CpuPool2d.cpp b/src/cpu/operators/CpuPool2d.cpp index a4ac871d48..eabbd5e0cc 100644 --- a/src/cpu/operators/CpuPool2d.cpp +++ b/src/cpu/operators/CpuPool2d.cpp @@ -39,7 +39,6 @@ namespace cpu { CpuPool2d::CpuPool2d() : _pooling_layer_kernel(), - _border_handler(), _asm_glue(), _is_global_pooling_layer(false), _data_layout(DataLayout::NCHW), @@ -86,28 +85,6 @@ void CpuPool2d::configure(ITensorInfo *src, ITensorInfo *dst, const PoolingLayer auto k = std::make_unique<kernels::CpuPool2dKernel>(); k->configure(src, dst, pool_info, indices); _pooling_layer_kernel = std::move(k); - - switch(_data_layout) - { - case DataLayout::NCHW: - { - // Configure border depending on operation required (quantize border in case of asymmetric data_type) - BorderMode border_mode = (!indices && pool_info.pool_type == PoolingType::MAX) ? BorderMode::REPLICATE : BorderMode::CONSTANT; - PixelValue zero_value((indices) ? std::numeric_limits<int>::min() : 0.f); - if(is_data_type_quantized_asymmetric(src->data_type()) && !pool_info.exclude_padding) - { - zero_value = PixelValue(0, src->data_type(), src->quantization_info()); - } - auto b = std::make_unique<NEFillBorderKernel>(); - b->configure(src, _pooling_layer_kernel->border_size(), border_mode, zero_value); - _border_handler = std::move(b); - break; - } - case DataLayout::NHWC: - break; - default: - ARM_COMPUTE_ERROR("Data layout not supported"); - } } } @@ -137,14 +114,9 @@ void CpuPool2d::run(ITensorPack &tensors) switch(_data_layout) { case DataLayout::NCHW: - // Fill border - NEScheduler::get().schedule_op(_border_handler.get(), Window::DimY, _border_handler->window(), tensors); - - // Run pooling layer NEScheduler::get().schedule_op(_pooling_layer_kernel.get(), _is_global_pooling_layer ? Window::DimZ : Window::DimY, _pooling_layer_kernel->window(), tensors); break; case DataLayout::NHWC: - // Run pooling layer NEScheduler::get().schedule_op(_pooling_layer_kernel.get(), Window::DimX, _pooling_layer_kernel->window(), tensors); break; default: diff --git a/src/cpu/operators/CpuPool2d.h b/src/cpu/operators/CpuPool2d.h index 471637164f..02c2609a6a 100644 --- a/src/cpu/operators/CpuPool2d.h +++ b/src/cpu/operators/CpuPool2d.h @@ -73,7 +73,6 @@ public: private: std::unique_ptr<INEKernel> _pooling_layer_kernel; - std::unique_ptr<INEKernel> _border_handler; std::unique_ptr<INEKernel> _asm_glue; bool _is_global_pooling_layer; |