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| author | Pablo Marquez Tello <pablo.tello@arm.com> | 2023-10-13 10:03:58 +0100 |
|---|---|---|
| committer | Pablo Marquez Tello <pablo.tello@arm.com> | 2023-10-20 10:59:09 +0000 |
| commit | 074b985f3855193bb47fb4055abb6b12f09f48d7 (patch) | |
| tree | 0c2308f1015d25f0b05beb07aec2497bcfb2be67 /src/cpu/kernels/fuse_batch_normalization/generic/fp16.cpp | |
| parent | 0fa92b849fd4892a341a3cda5e2ff9092093f841 (diff) | |
| download | ComputeLibrary-074b985f3855193bb47fb4055abb6b12f09f48d7.tar.gz | |
FuseBatchNorm changes to enable fp16 in armv8a multi_isa builds
* FP16 kernels must be instantiated in fp16.cpp.
* Partially resolves MLCE-1102
Change-Id: Ie652203876a0ac12b025e96d20990b6efb21e772
Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/10477
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Jakub Sujak <jakub.sujak@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/kernels/fuse_batch_normalization/generic/fp16.cpp')
| -rw-r--r-- | src/cpu/kernels/fuse_batch_normalization/generic/fp16.cpp | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/src/cpu/kernels/fuse_batch_normalization/generic/fp16.cpp b/src/cpu/kernels/fuse_batch_normalization/generic/fp16.cpp index 2821af32ce..8f47ecba8f 100644 --- a/src/cpu/kernels/fuse_batch_normalization/generic/fp16.cpp +++ b/src/cpu/kernels/fuse_batch_normalization/generic/fp16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -43,6 +43,21 @@ void fused_batch_normalization_conv_f16(const ITensor *conv_weights, return fused_batch_normalization_conv<float16_t>(conv_weights, conv_bias, fused_weights, fused_bias, bn_mean, bn_var, bn_beta, bn_gamma, epsilon, window); } + +void fused_batch_normalization_dwc_nchw_f16(const ITensor *dwc_weights, + const ITensor *dwc_bias, + ITensor *fused_weights, + ITensor *fused_bias, + const ITensor *bn_mean, + const ITensor *bn_var, + const ITensor *bn_beta, + const ITensor *bn_gamma, + float epsilon, + const Window &window) +{ + return fused_batch_normalization_dwc_nchw<float16_t>(dwc_weights, dwc_bias, fused_weights, fused_bias, bn_mean, + bn_var, bn_beta, bn_gamma, epsilon, window); +} } // namespace cpu } // namespace arm_compute #endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ |