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| author | SiCong Li <sicong.li@arm.com> | 2023-05-17 13:46:13 +0100 |
|---|---|---|
| committer | SiCong Li <sicong.li@arm.com> | 2023-05-17 16:21:31 +0100 |
| commit | 3f70cd053573cb6140990ab619ead865f55f3139 (patch) | |
| tree | 6ed9cf0222c4b0ab1def1c9276bef41767accd36 /src/cpu/kernels/CpuActivationKernel.cpp | |
| parent | 81ca48606cea2220a83ae8d736d3935bcc17f854 (diff) | |
| download | ComputeLibrary-3f70cd053573cb6140990ab619ead865f55f3139.tar.gz | |
Move lut kernel to sve2 categoryv23.05branches/arm_compute_23_05
This specific Lut kernel uses sve2 instructions
Resolves: COMPMID-6268
Signed-off-by: SiCong Li <sicong.li@arm.com>
Change-Id: I44fa3812e96fa79b3d1e1e3a31d587581f59f0e1
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9675
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Reviewed-by: Jakub Sujak <jakub.sujak@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/kernels/CpuActivationKernel.cpp')
| -rw-r--r-- | src/cpu/kernels/CpuActivationKernel.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/kernels/CpuActivationKernel.cpp b/src/cpu/kernels/CpuActivationKernel.cpp index 04a9731f4a..20a8489cdd 100644 --- a/src/cpu/kernels/CpuActivationKernel.cpp +++ b/src/cpu/kernels/CpuActivationKernel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022 Arm Limited. + * Copyright (c) 2017-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -47,9 +47,9 @@ static const std::vector<CpuActivationKernel::ActivationKernel> available_kernel { #ifdef ARM_COMPUTE_ENABLE_SVE { - "sve_q8_activation_lut", - [](const ActivationDataTypeISASelectorData & data) { return ActivationLayerInfo::is_lut_supported(data.f, data.dt) && data.cpumodel == CPUModel::A510 && data.isa.sve; }, - REGISTER_QASYMM8_SVE(arm_compute::cpu::sve_q8_activation_lut) + "sve2_q8_activation_lut", + [](const ActivationDataTypeISASelectorData & data) { return ActivationLayerInfo::is_lut_supported(data.f, data.dt) && data.cpumodel == CPUModel::A510 && data.isa.sve2; }, + REGISTER_QASYMM8_SVE2(arm_compute::cpu::sve2_q8_activation_lut) }, #endif // ARM_COMPUTE_ENABLE_SVE #ifdef __aarch64__ |