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author | Manuel Bottini <manuel.bottini@arm.com> | 2021-03-23 11:50:34 +0000 |
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committer | Manuel Bottini <manuel.bottini@arm.com> | 2021-04-06 11:28:16 +0000 |
commit | ca62c6f53eb7244e6fed9f7e932608aa2496d9eb (patch) | |
tree | e5c7630c40d9f009e9baef4e849c6c7cc6ca90a7 /src/core | |
parent | 4ed7b39dbbe8ccc6267a9eacefca51717c3b3e10 (diff) | |
download | ComputeLibrary-ca62c6f53eb7244e6fed9f7e932608aa2496d9eb.tar.gz |
Mixed data-layout testing on high priority operators
Change data layouts after the configure in validation tests for:
- Scale
- Pooling
- FullyConnected
- DepthwiseConvolution
- DirectConvolution
- FFTConvolution
- WinogradConvolution
- GEMMConvolution (Indirect GEMM included)
Extending fixtures
Fixes for new mixed data layout tests
Resolves: COMPMID-4162
Change-Id: I2f2eb2075f7e24ab3872249d88cadb57b82c5dde
Signed-off-by: Manuel Bottini <manuel.bottini@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5326
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Diffstat (limited to 'src/core')
-rw-r--r-- | src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp | 11 | ||||
-rw-r--r-- | src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h | 1 | ||||
-rw-r--r-- | src/core/cpu/kernels/pooling/neon/fp16.cpp | 4 | ||||
-rw-r--r-- | src/core/cpu/kernels/pooling/neon/fp32.cpp | 4 | ||||
-rw-r--r-- | src/core/cpu/kernels/pooling/neon/list.h | 4 | ||||
-rw-r--r-- | src/core/cpu/kernels/pooling/neon/nchw/all.cpp | 2 | ||||
-rw-r--r-- | src/core/cpu/kernels/scale/sve/qasymm8.cpp | 7 | ||||
-rw-r--r-- | src/core/cpu/kernels/scale/sve/qasymm8_signed.cpp | 7 |
8 files changed, 20 insertions, 20 deletions
diff --git a/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp b/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp index 09f99748bf..98b76c7db3 100644 --- a/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp +++ b/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp @@ -1217,7 +1217,7 @@ void NEDirectConvolutionLayerKernel::convolve_nhwc(const Window &window) NEDirectConvolutionLayerKernel::NEDirectConvolutionLayerKernel() : _input(nullptr), _weights(nullptr), _output(nullptr), _conv_info(), _border_size(0), _kernel_size(0), _num_weight_elems_read_per_row(0), _num_elems_read_per_iteration(0), - _num_elems_written_per_iteration(0) + _num_elems_written_per_iteration(0), _data_layout() { } @@ -1234,13 +1234,14 @@ void NEDirectConvolutionLayerKernel::configure(const ITensor *input, const ITens _weights = weights; _output = output; _conv_info = conv_info; - _kernel_size = weights->info()->dimension(get_data_layout_dimension_index(weights->info()->data_layout(), DataLayoutDimension::WIDTH)); + _data_layout = _input->info()->data_layout(); + _kernel_size = weights->info()->dimension(get_data_layout_dimension_index(_data_layout, DataLayoutDimension::WIDTH)); const unsigned int conv_pad_left = conv_info.pad_left(); const unsigned int conv_pad_top = conv_info.pad_top(); const unsigned int conv_pad_right = conv_info.pad_right(); const unsigned int conv_pad_bottom = conv_info.pad_bottom(); - if(_input->info()->data_layout() == DataLayout::NCHW) + if(_data_layout == DataLayout::NCHW) { _border_size = BorderSize(conv_pad_top, conv_pad_right, conv_pad_bottom, conv_pad_left); } @@ -1294,9 +1295,9 @@ void NEDirectConvolutionLayerKernel::run(const Window &window, const ThreadInfo ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(INEKernel::window(), window); ARM_COMPUTE_ERROR_ON(_input->buffer() == nullptr); - const int kernel_size = _weights->info()->dimension(get_data_layout_dimension_index(_weights->info()->data_layout(), DataLayoutDimension::WIDTH)); + const int kernel_size = _weights->info()->dimension(get_data_layout_dimension_index(_data_layout, DataLayoutDimension::WIDTH)); - if(_input->info()->data_layout() == DataLayout::NCHW) + if(_data_layout == DataLayout::NCHW) { switch(kernel_size) { diff --git a/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h b/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h index 258def77a3..259eb683f6 100644 --- a/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h +++ b/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h @@ -103,6 +103,7 @@ private: unsigned int _num_weight_elems_read_per_row; unsigned int _num_elems_read_per_iteration; unsigned int _num_elems_written_per_iteration; + DataLayout _data_layout; }; } // namespace arm_compute #endif /*ARM_COMPUTE_NEDIRECTCONVOLUTIONLAYERKERNEL_H */ diff --git a/src/core/cpu/kernels/pooling/neon/fp16.cpp b/src/core/cpu/kernels/pooling/neon/fp16.cpp index 314be3704e..1ecceafe86 100644 --- a/src/core/cpu/kernels/pooling/neon/fp16.cpp +++ b/src/core/cpu/kernels/pooling/neon/fp16.cpp @@ -93,7 +93,7 @@ void pooling2_f16_maxpool_indices(const ITensor *src, ITensor *dst0, ITensor *ds // Store result vst1q_f16(reinterpret_cast<float16_t *>(out.ptr()) + x_off, vres); - const uint32_t offset_base = offset_no_padding<float16_t>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y); + const uint32_t offset_base = offset_no_padding<float16_t>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y, DataLayout::NHWC); const uint32_t offset_x0 = (uint32_t)offset_base / sizeof(float16_t) + x_off; const uint32_t offset_x1 = (uint32_t)offset_x0 + in_stride_y / sizeof(float16_t) - pad_right; const uint32_t offset_x2 = (uint32_t)offset_x0 + in_stride_z / sizeof(float16_t) - pad_right * src->info()->tensor_shape()[1]; @@ -132,7 +132,7 @@ void pooling2_f16_maxpool_indices(const ITensor *src, ITensor *dst0, ITensor *ds // Store result *(reinterpret_cast<float16_t *>(out.ptr()) + x_off) = res; - const uint32_t offset_base = offset_no_padding<float16_t>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y); + const uint32_t offset_base = offset_no_padding<float16_t>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y, DataLayout::NHWC); const uint32_t offset_x0 = (uint32_t)offset_base / sizeof(float16_t) + x_off; const uint32_t offset_x1 = (uint32_t)offset_x0 + in_stride_y / sizeof(float16_t) - pad_right; const uint32_t offset_x2 = (uint32_t)offset_x0 + in_stride_z / sizeof(float16_t) - pad_right * src->info()->tensor_shape()[1]; diff --git a/src/core/cpu/kernels/pooling/neon/fp32.cpp b/src/core/cpu/kernels/pooling/neon/fp32.cpp index e319047d76..a2bd4a6bb3 100644 --- a/src/core/cpu/kernels/pooling/neon/fp32.cpp +++ b/src/core/cpu/kernels/pooling/neon/fp32.cpp @@ -95,7 +95,7 @@ void pooling2_f32_maxpool_indices(const ITensor *src, ITensor *dst0, ITensor *ds // Store result vst1q_f32(reinterpret_cast<float *>(out.ptr()) + x_off, vres); - const uint32_t offset_base = offset_no_padding<float>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y); + const uint32_t offset_base = offset_no_padding<float>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y, DataLayout::NHWC); const uint32_t offset_x0 = (uint32_t)offset_base / sizeof(float) + x_off; const uint32_t offset_x1 = (uint32_t)offset_x0 + in_stride_y / sizeof(float) - pad_right; const uint32_t offset_x2 = (uint32_t)offset_x0 + in_stride_z / sizeof(float) - pad_right * src->info()->tensor_shape()[1]; @@ -124,7 +124,7 @@ void pooling2_f32_maxpool_indices(const ITensor *src, ITensor *dst0, ITensor *ds // Store result *(reinterpret_cast<float *>(out.ptr()) + x_off) = res; - const uint32_t offset_base = offset_no_padding<float>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y); + const uint32_t offset_base = offset_no_padding<float>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y, DataLayout::NHWC); const uint32_t offset_x0 = (uint32_t)offset_base / sizeof(float) + x_off; const uint32_t offset_x1 = (uint32_t)offset_x0 + in_stride_y / sizeof(float) - pad_right; const uint32_t offset_x2 = (uint32_t)offset_x0 + in_stride_z / sizeof(float) - pad_right * src->info()->tensor_shape()[1]; diff --git a/src/core/cpu/kernels/pooling/neon/list.h b/src/core/cpu/kernels/pooling/neon/list.h index 3435ee6724..bec1536f61 100644 --- a/src/core/cpu/kernels/pooling/neon/list.h +++ b/src/core/cpu/kernels/pooling/neon/list.h @@ -59,7 +59,7 @@ DECLARE_POOLING_KERNEL(poolingMxN_fp32_neon_nchw); #undef DECLARE_POOLING_KERNEL template <typename T> -inline uint32_t offset_no_padding(uint32_t padded_offset, const Coordinates &id, const ITensorInfo &info, int pool_stride_x, int pool_stride_y) +inline uint32_t offset_no_padding(uint32_t padded_offset, const Coordinates &id, const ITensorInfo &info, int pool_stride_x, int pool_stride_y, DataLayout data_layout) { const int pad_left = info.padding().left; const int pad_right = info.padding().right; @@ -70,7 +70,7 @@ inline uint32_t offset_no_padding(uint32_t padded_offset, const Coordinates &id, const int pad_horiz = pad_left + pad_right; const int pad_vert = pad_top + pad_bottom; - if(info.data_layout() == DataLayout::NCHW) + if(data_layout == DataLayout::NCHW) { const uint32_t offset_base = padded_offset - sizeof(T) * pad_horiz * id.y() * pool_stride_y /* subtract padding elems per row */ diff --git a/src/core/cpu/kernels/pooling/neon/nchw/all.cpp b/src/core/cpu/kernels/pooling/neon/nchw/all.cpp index 47ac7b4f7f..80eac684aa 100644 --- a/src/core/cpu/kernels/pooling/neon/nchw/all.cpp +++ b/src/core/cpu/kernels/pooling/neon/nchw/all.cpp @@ -150,7 +150,7 @@ void pooling2_nchw_maxpool_indices(const ITensor *src, ITensor *dst0, ITensor *d *(reinterpret_cast<T *>(out.ptr())) = static_cast<T>(vget_lane_f32(max_data, 0)); // Calculate max data indice, which will be used in max unpool. - const uint32_t offset_base = offset_no_padding<T>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y); + const uint32_t offset_base = offset_no_padding<T>(in.offset(), id, *src->info(), pool_stride_x, pool_stride_y, DataLayout::NCHW); const uint32_t offset_top = (uint32_t)(offset_base / sizeof(T)); const uint32_t offset_bottom = offset_top + in_stride_y / sizeof(T) - pad_right - pad_left; const uint32x2_t voffset_top = { offset_top, offset_top + 1u }; diff --git a/src/core/cpu/kernels/scale/sve/qasymm8.cpp b/src/core/cpu/kernels/scale/sve/qasymm8.cpp index c475ad615c..c041f14b22 100644 --- a/src/core/cpu/kernels/scale/sve/qasymm8.cpp +++ b/src/core/cpu/kernels/scale/sve/qasymm8.cpp @@ -89,10 +89,9 @@ void qasymm8_sve_scale_bilinear(const ITensor *src, ITensor *dst, const ITensor BorderMode border_mode, PixelValue constant_border_value, float sampling_offset, bool align_corners, const Window &window) { - // Get data layout and width/height indices - const DataLayout data_layout = src->info()->data_layout(); - const int idx_width = get_data_layout_dimension_index(data_layout, DataLayoutDimension::WIDTH); - const int idx_height = get_data_layout_dimension_index(data_layout, DataLayoutDimension::HEIGHT); + // Data layout is NHWC + const int idx_width = 1; + const int idx_height = 2; // Compute the ratio between source height and destination height const auto hr = scale_utils::calculate_resize_ratio(src->info()->dimension(idx_height), dst->info()->dimension(idx_height), align_corners); diff --git a/src/core/cpu/kernels/scale/sve/qasymm8_signed.cpp b/src/core/cpu/kernels/scale/sve/qasymm8_signed.cpp index b39b75abba..9df4301fe3 100644 --- a/src/core/cpu/kernels/scale/sve/qasymm8_signed.cpp +++ b/src/core/cpu/kernels/scale/sve/qasymm8_signed.cpp @@ -89,10 +89,9 @@ void qasymm8_signed_sve_scale_bilinear(const ITensor *src, ITensor *dst, const I BorderMode border_mode, PixelValue constant_border_value, float sampling_offset, bool align_corners, const Window &window) { - // Get data layout and width/height indices - const DataLayout data_layout = src->info()->data_layout(); - const int idx_width = get_data_layout_dimension_index(data_layout, DataLayoutDimension::WIDTH); - const int idx_height = get_data_layout_dimension_index(data_layout, DataLayoutDimension::HEIGHT); + // Data layout is NHWC + const int idx_width = 1; + const int idx_height = 2; // Compute the ratio between source height and destination height const auto hr = scale_utils::calculate_resize_ratio(src->info()->dimension(idx_height), dst->info()->dimension(idx_height), align_corners); |