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| author | Pablo Marquez Tello <pablo.tello@arm.com> | 2023-11-21 10:10:01 +0000 |
|---|---|---|
| committer | Pablo Marquez Tello <pablo.tello@arm.com> | 2023-11-27 17:16:45 +0000 |
| commit | 8d4cdd43a74574e0f99f83f1adb1d391c0c85abe (patch) | |
| tree | 614000681778c2f390897888ce69dfdd62561799 /src/core/NEON/kernels/batchnormalization/impl/list.h | |
| parent | 835577e1477003789c392d8faab4a3bb8f4040ba (diff) | |
| download | ComputeLibrary-8d4cdd43a74574e0f99f83f1adb1d391c0c85abe.tar.gz | |
BatchNorm changes to enable fp16 in armv8a multi_isa builds
* Moved NCHW kernels fp16 and fp32 to their corresponding files
src/cpu/kernels/fuse_batch_normalization/nchw/neon/fp16.cpp and
src/cpu/kernels/fuse_batch_normalization/nchw/neon/fp32.cpp
* Changes in filelist.json to include the new fp16 and fp32 files
* Moved the template batch_normalization_nchw to impl.h as we
need to instantiate it from fp16.cpp and fp32.cpp
* Pooling layer: removed the guard __ARM_FEATURE_FP16_VECTOR_ARITHMETIC that
prevented the FP16 kernel execution.
* Partially resolves MLCE-1102
Change-Id: Ia8c85e9ffb76c9e387f9ae2685e5df5e52c8dc27
Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/10777
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/batchnormalization/impl/list.h')
| -rw-r--r-- | src/core/NEON/kernels/batchnormalization/impl/list.h | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/src/core/NEON/kernels/batchnormalization/impl/list.h b/src/core/NEON/kernels/batchnormalization/impl/list.h index cbf540bd71..c619788125 100644 --- a/src/core/NEON/kernels/batchnormalization/impl/list.h +++ b/src/core/NEON/kernels/batchnormalization/impl/list.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Arm Limited. + * Copyright (c) 2020, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,8 +21,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#ifndef SRC_CORE_NEON_KERNELS_BATCH_NORMALIZATION_LIST_H -#define SRC_CORE_NEON_KERNELS_BATCH_NORMALIZATION_LIST_H +#ifndef ACL_SRC_CORE_NEON_KERNELS_BATCHNORMALIZATION_IMPL_LIST_H +#define ACL_SRC_CORE_NEON_KERNELS_BATCHNORMALIZATION_IMPL_LIST_H namespace arm_compute { @@ -37,8 +37,23 @@ DECLARE_BATCH_NORMALIZATION_KERNEL(fp16_sve_batch_normalization); DECLARE_BATCH_NORMALIZATION_KERNEL(fp32_neon_batch_normalization); DECLARE_BATCH_NORMALIZATION_KERNEL(fp32_sve_batch_normalization); -#undef DECLARE_ACTIVATION_KERNEL +#define DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(func_name) \ + void func_name(const Window &window, ITensor *input, ITensor *output, const ITensor *mean, const ITensor *var, \ + const ITensor *beta, const ITensor *gamma, float epsilon, ActivationLayerInfo act_info) + +DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(fp16_batch_normalization_nchw_non_fused); +DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(fp32_batch_normalization_nchw_non_fused); +DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(fp16_batch_normalization_nchw_non_fused_relu); +DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(fp16_batch_normalization_nchw_non_fused_brelu); +DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(fp16_batch_normalization_nchw_non_fused_lubrelu); +DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(fp32_batch_normalization_nchw_non_fused_relu); +DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(fp32_batch_normalization_nchw_non_fused_brelu); +DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL(fp32_batch_normalization_nchw_non_fused_lubrelu); + +#undef DECLARE_BATCH_NORMALIZATION_KERNEL +#undef DECLARE_BATCH_NORMALIZATION_NCHW_KERNEL + } // namespace cpu } // namespace arm_compute -#endif /* SRC_CORE_NEON_KERNELS_BATCH_NORMALIZATION_LIST_H */ +#endif // ACL_SRC_CORE_NEON_KERNELS_BATCHNORMALIZATION_IMPL_LIST_H |