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author | Michael Tyler <michael.tyler@arm.com> | 2023-02-01 16:37:07 +0000 |
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committer | michael.tyler <michael.tyler@arm.com> | 2023-02-08 15:33:26 +0000 |
commit | 7d9a626aaba9837cb82d189a9c4f0bcef58825bb (patch) | |
tree | e3d8cfeb7f8539cca3a8bf2f1a8f412d25d89041 /src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp | |
parent | 4e2bbbbb23e6f4bd452f7f865e51228e1f51efec (diff) | |
download | ComputeLibrary-7d9a626aaba9837cb82d189a9c4f0bcef58825bb.tar.gz |
Update CPU kernels to remove x19 and w19
Resolves: COMPMID-5805
Change-Id: Idf720bbb136474810086f5089c5ed23b3f79835a
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9081
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp')
-rw-r--r-- | src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp | 92 |
1 files changed, 46 insertions, 46 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp index 39c49990eb..9eb4075677 100644 --- a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -10,16 +10,16 @@ * sell copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. */ #pragma once @@ -43,69 +43,69 @@ void sme_transpose_interleave_2VL_1x4(uint8_t *out, const uint8_t *in, size_t wi ".inst 0xd503477f // SMSTART ZA\n" "ptrue p1.b\n" "1:" // Main row loop: Head - "mov x25, %x[in]\n" + "mov x26, %x[in]\n" + "add x25, x26, %x[in_stride]\n" "add x24, x25, %x[in_stride]\n" "add x23, x24, %x[in_stride]\n" - "add x22, x23, %x[in_stride]\n" "cmp %x[height], #0x3\n" - "add %x[in], x22, %x[in_stride]\n" - "csel x22, x22, %x[pad_row], GT\n" - "csel x23, x23, %x[pad_row], GE\n" + "add %x[in], x23, %x[in_stride]\n" + "csel x23, x23, %x[pad_row], GT\n" + "csel x24, x24, %x[pad_row], GE\n" "cmp %x[height], #0x1\n" - "mov x21, %x[width]\n" - "cntb x20\n" - "csel x24, x24, %x[pad_row], GT\n" - "cmp x21, x20\n" - "mov x19, %x[out]\n" + "mov x22, %x[width]\n" + "cntb x21\n" + "csel x25, x25, %x[pad_row], GT\n" + "cmp x22, x21\n" + "mov x20, %x[out]\n" "sub %x[height], %x[height], #0x4\n" "blt 3f\n" "2:" // Main row loop: Unroll column loop - "ld1b { z17.b }, p1/Z, [x25]\n" - "sub x21, x21, x20\n" - "cmp x21, x20\n" - "ld1b { z18.b }, p1/Z, [x24]\n" + "ld1b { z17.b }, p1/Z, [x26]\n" + "sub x22, x22, x21\n" + "cmp x22, x21\n" + "ld1b { z18.b }, p1/Z, [x25]\n" + "addvl x26, x26, #1\n" "addvl x25, x25, #1\n" - "addvl x24, x24, #1\n" - "ld1b { z16.b }, p1/Z, [x23]\n" + "ld1b { z16.b }, p1/Z, [x24]\n" "zip1 z20.b, z17.b, z16.b\n" "zip2 z19.b, z17.b, z16.b\n" - "addvl x23, x23, #1\n" - "ld1b { z17.b }, p1/Z, [x22]\n" + "addvl x24, x24, #1\n" + "ld1b { z17.b }, p1/Z, [x23]\n" "zip1 z16.b, z18.b, z17.b\n" "zip2 z18.b, z18.b, z17.b\n" - "addvl x22, x22, #1\n" + "addvl x23, x23, #1\n" "zip1 z17.b, z20.b, z16.b\n" "zip2 z16.b, z20.b, z16.b\n" - "st1b { z17.b }, p1, [x19]\n" - "st1b { z16.b }, p1, [x19, #1, MUL VL]\n" - "add x19, x19, %x[out_stride]\n" + "st1b { z17.b }, p1, [x20]\n" + "st1b { z16.b }, p1, [x20, #1, MUL VL]\n" + "add x20, x20, %x[out_stride]\n" "zip1 z17.b, z19.b, z18.b\n" "zip2 z16.b, z19.b, z18.b\n" - "st1b { z17.b }, p1, [x19]\n" - "st1b { z16.b }, p1, [x19, #1, MUL VL]\n" - "add x19, x19, %x[out_stride]\n" + "st1b { z17.b }, p1, [x20]\n" + "st1b { z16.b }, p1, [x20, #1, MUL VL]\n" + "add x20, x20, %x[out_stride]\n" "bge 2b\n" "3:" // Main row loop: Unroll column loop skip - "cbz x21, 5f\n" + "cbz x22, 5f\n" "4:" // Main row loop: Column loop - "whilelt p0.b, XZR, x21\n" - "ld1b { z18.b }, p0/Z, [x25]\n" - "decw x21, ALL, MUL #2\n" - "ld1b { z17.b }, p0/Z, [x24]\n" - "cmp x21, #0x0\n" - "incd x25, ALL, MUL #4\n" - "ld1b { z16.b }, p0/Z, [x23]\n" + "whilelt p0.b, XZR, x22\n" + "ld1b { z18.b }, p0/Z, [x26]\n" + "decw x22, ALL, MUL #2\n" + "ld1b { z17.b }, p0/Z, [x25]\n" + "cmp x22, #0x0\n" + "incd x26, ALL, MUL #4\n" + "ld1b { z16.b }, p0/Z, [x24]\n" "zip1 z18.b, z18.b, z16.b\n" + "incd x25, ALL, MUL #4\n" "incd x24, ALL, MUL #4\n" - "incd x23, ALL, MUL #4\n" - "ld1b { z16.b }, p0/Z, [x22]\n" + "ld1b { z16.b }, p0/Z, [x23]\n" "zip1 z16.b, z17.b, z16.b\n" - "incd x22, ALL, MUL #4\n" + "incd x23, ALL, MUL #4\n" "zip1 z17.b, z18.b, z16.b\n" "zip2 z16.b, z18.b, z16.b\n" - "st1b { z17.b }, p1, [x19]\n" - "st1b { z16.b }, p1, [x19, #1, MUL VL]\n" - "add x19, x19, %x[out_stride]\n" + "st1b { z17.b }, p1, [x20]\n" + "st1b { z16.b }, p1, [x20, #1, MUL VL]\n" + "add x20, x20, %x[out_stride]\n" "bgt 4b\n" "5:" // Main row loop: Column loop skip "cmp %x[height], #0x1\n" @@ -114,7 +114,7 @@ void sme_transpose_interleave_2VL_1x4(uint8_t *out, const uint8_t *in, size_t wi ".inst 0xd503467f // SMSTOP\n" : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } |