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author | Georgios Pinitas <georgios.pinitas@arm.com> | 2019-06-27 17:00:52 +0100 |
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committer | Georgios Pinitas <georgios.pinitas@arm.com> | 2019-07-26 11:55:15 +0000 |
commit | cfa2bba98169cb5ab1945462514be1b6badf7d98 (patch) | |
tree | 1635e6e9463e9798c7195f0aa71b5df3f2650df1 /src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_12way_half_to_float.hpp | |
parent | f59b16f42ef68bde877b70816ffb953d64c8baa3 (diff) | |
download | ComputeLibrary-cfa2bba98169cb5ab1945462514be1b6badf7d98.tar.gz |
COMPMID-2178: Update GEMM assembly code.
Perform offset reduction and requantization within the assembly wrapper.
Change-Id: I5d5b3e1f6f9ef4c71805362c57f88ff199c027a3
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Reviewed-on: https://review.mlplatform.org/c/1541
Comments-Addressed: Pablo Marquez <pablo.tello@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_12way_half_to_float.hpp')
-rw-r--r-- | src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_12way_half_to_float.hpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_12way_half_to_float.hpp b/src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_12way_half_to_float.hpp index 46b4bf5149..8992c1010d 100644 --- a/src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_12way_half_to_float.hpp +++ b/src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_12way_half_to_float.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 ARM Limited. + * Copyright (c) 2017-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -59,7 +59,7 @@ inline void TransposeInterleaveCommon<12, __fp16, float>::moveblock_1x2(const __ "FCVTL v3.4s, v3.4h\n" "STP q2, q3, [%[out], #32]\n" ASM_PREFETCH("[%[in1], #192]") - "LDR d5, [%[in1]], #16\n" + "LDR d5, [%[in1]], #8\n" "FCVTL v5.4s, v5.4h\n" "STP q4, q5, [%[out], #64]\n" : [in0] "+r" (in0), [in1] "+r" (in1), [out] "+r" (out) |