Update CPU kernel implementations and guard directives

Resolves COMPMID-6023

Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>

1 files changed, 62 insertions, 58 deletions

diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp
index 9d1c0c3728..c7f32ff7a9 100644
--- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp
+++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp
@@ -28,8 +28,12 @@
 namespace arm_gemm {
 
 void sve_interleaved_fp32_mla_8x3VL(
-    const float *Apanel, const float *Bpanel,
-    float *Cpanel, int ablocks, int bblocks, int K) {
+    const float *Apanel,
+    const float *Bpanel,
+    float *Cpanel,
+    int ablocks,
+    int bblocks,
+    int K) {
 
     struct KernelArgs {
         size_t K = {};
@@ -84,10 +88,10 @@ void sve_interleaved_fp32_mla_8x3VL(
       "3:"  // main loop head
       "fmla z8.s, z4.s, z0.s[0]\n"
       "fmla z11.s, z4.s, z0.s[1]\n"
-      "ld1rqw { z2.s }, p0/Z, [%x[Apanel], #32]\n"
+      "ld1rqw { z3.s }, p0/Z, [%x[Apanel], #32]\n"
       "fmla z14.s, z4.s, z0.s[2]\n"
       "fmla z17.s, z4.s, z0.s[3]\n"
-      "ld1rqw { z3.s }, p0/Z, [%x[Apanel], #48]\n"
+      "ld1rqw { z7.s }, p0/Z, [%x[Apanel], #48]\n"
       "fmla z20.s, z4.s, z1.s[0]\n"
       "fmla z23.s, z4.s, z1.s[1]\n"
       "sub x20, x20, #0x2\n"
@@ -114,35 +118,35 @@ void sve_interleaved_fp32_mla_8x3VL(
       "fmla z25.s, z6.s, z1.s[1]\n"
       "fmla z28.s, z6.s, z1.s[2]\n"
       "fmla z31.s, z6.s, z1.s[3]\n"
-      "ld1w { z6.s }, p0/Z, [x22, #5, MUL VL]\n"
+      "ld1w { z2.s }, p0/Z, [x22, #5, MUL VL]\n"
       "addvl x22, x22, #6\n"
-      "fmla z8.s, z4.s, z2.s[0]\n"
-      "fmla z11.s, z4.s, z2.s[1]\n"
+      "fmla z8.s, z4.s, z3.s[0]\n"
+      "fmla z11.s, z4.s, z3.s[1]\n"
       "ld1rqw { z1.s }, p0/Z, [%x[Apanel], #16]\n"
-      "fmla z14.s, z4.s, z2.s[2]\n"
-      "fmla z17.s, z4.s, z2.s[3]\n"
-      "fmla z20.s, z4.s, z3.s[0]\n"
-      "fmla z23.s, z4.s, z3.s[1]\n"
-      "fmla z26.s, z4.s, z3.s[2]\n"
-      "fmla z29.s, z4.s, z3.s[3]\n"
+      "fmla z14.s, z4.s, z3.s[2]\n"
+      "fmla z17.s, z4.s, z3.s[3]\n"
+      "fmla z20.s, z4.s, z7.s[0]\n"
+      "fmla z23.s, z4.s, z7.s[1]\n"
+      "fmla z26.s, z4.s, z7.s[2]\n"
+      "fmla z29.s, z4.s, z7.s[3]\n"
       "ld1w { z4.s }, p0/Z, [x22]\n"
-      "fmla z9.s, z5.s, z2.s[0]\n"
-      "fmla z12.s, z5.s, z2.s[1]\n"
-      "fmla z15.s, z5.s, z2.s[2]\n"
-      "fmla z18.s, z5.s, z2.s[3]\n"
-      "fmla z21.s, z5.s, z3.s[0]\n"
-      "fmla z24.s, z5.s, z3.s[1]\n"
-      "fmla z27.s, z5.s, z3.s[2]\n"
-      "fmla z30.s, z5.s, z3.s[3]\n"
+      "fmla z9.s, z5.s, z3.s[0]\n"
+      "fmla z12.s, z5.s, z3.s[1]\n"
+      "fmla z15.s, z5.s, z3.s[2]\n"
+      "fmla z18.s, z5.s, z3.s[3]\n"
+      "fmla z21.s, z5.s, z7.s[0]\n"
+      "fmla z24.s, z5.s, z7.s[1]\n"
+      "fmla z27.s, z5.s, z7.s[2]\n"
+      "fmla z30.s, z5.s, z7.s[3]\n"
       "ld1w { z5.s }, p0/Z, [x22, #1, MUL VL]\n"
-      "fmla z10.s, z6.s, z2.s[0]\n"
-      "fmla z13.s, z6.s, z2.s[1]\n"
-      "fmla z16.s, z6.s, z2.s[2]\n"
-      "fmla z19.s, z6.s, z2.s[3]\n"
-      "fmla z22.s, z6.s, z3.s[0]\n"
-      "fmla z25.s, z6.s, z3.s[1]\n"
-      "fmla z28.s, z6.s, z3.s[2]\n"
-      "fmla z31.s, z6.s, z3.s[3]\n"
+      "fmla z10.s, z2.s, z3.s[0]\n"
+      "fmla z13.s, z2.s, z3.s[1]\n"
+      "fmla z16.s, z2.s, z3.s[2]\n"
+      "fmla z19.s, z2.s, z3.s[3]\n"
+      "fmla z22.s, z2.s, z7.s[0]\n"
+      "fmla z25.s, z2.s, z7.s[1]\n"
+      "fmla z28.s, z2.s, z7.s[2]\n"
+      "fmla z31.s, z2.s, z7.s[3]\n"
       "ld1w { z6.s }, p0/Z, [x22, #2, MUL VL]\n"
       "bge 3b\n"
       "4:"  // main loop skip
@@ -173,37 +177,37 @@ void sve_interleaved_fp32_mla_8x3VL(
       "fmla z28.s, z6.s, z1.s[2]\n"
       "fmla z31.s, z6.s, z1.s[3]\n"
       "cbz x20, 5f\n"
-      "ld1rqw { z0.s }, p0/Z, [%x[Apanel]]\n"
-      "ld1rqw { z1.s }, p0/Z, [%x[Apanel], #16]\n"
+      "ld1rqw { z4.s }, p0/Z, [%x[Apanel]]\n"
+      "ld1rqw { z3.s }, p0/Z, [%x[Apanel], #16]\n"
       "add %x[Apanel], %x[Apanel], #0x20\n"
-      "ld1w { z7.s }, p0/Z, [x22]\n"
-      "ld1w { z4.s }, p0/Z, [x22, #1, MUL VL]\n"
-      "fmla z8.s, z7.s, z0.s[0]\n"
-      "ld1w { z5.s }, p0/Z, [x22, #2, MUL VL]\n"
-      "fmla z11.s, z7.s, z0.s[1]\n"
-      "fmla z14.s, z7.s, z0.s[2]\n"
-      "fmla z17.s, z7.s, z0.s[3]\n"
-      "fmla z20.s, z7.s, z1.s[0]\n"
+      "ld1w { z2.s }, p0/Z, [x22]\n"
+      "ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n"
+      "fmla z8.s, z2.s, z4.s[0]\n"
+      "ld1w { z0.s }, p0/Z, [x22, #2, MUL VL]\n"
+      "fmla z11.s, z2.s, z4.s[1]\n"
+      "fmla z14.s, z2.s, z4.s[2]\n"
+      "fmla z17.s, z2.s, z4.s[3]\n"
+      "fmla z20.s, z2.s, z3.s[0]\n"
       "addvl x22, x22, #3\n"
-      "fmla z23.s, z7.s, z1.s[1]\n"
-      "fmla z26.s, z7.s, z1.s[2]\n"
-      "fmla z29.s, z7.s, z1.s[3]\n"
-      "fmla z9.s, z4.s, z0.s[0]\n"
-      "fmla z12.s, z4.s, z0.s[1]\n"
-      "fmla z15.s, z4.s, z0.s[2]\n"
-      "fmla z18.s, z4.s, z0.s[3]\n"
-      "fmla z21.s, z4.s, z1.s[0]\n"
-      "fmla z24.s, z4.s, z1.s[1]\n"
-      "fmla z27.s, z4.s, z1.s[2]\n"
-      "fmla z30.s, z4.s, z1.s[3]\n"
-      "fmla z10.s, z5.s, z0.s[0]\n"
-      "fmla z13.s, z5.s, z0.s[1]\n"
-      "fmla z16.s, z5.s, z0.s[2]\n"
-      "fmla z19.s, z5.s, z0.s[3]\n"
-      "fmla z22.s, z5.s, z1.s[0]\n"
-      "fmla z25.s, z5.s, z1.s[1]\n"
-      "fmla z28.s, z5.s, z1.s[2]\n"
-      "fmla z31.s, z5.s, z1.s[3]\n"
+      "fmla z23.s, z2.s, z3.s[1]\n"
+      "fmla z26.s, z2.s, z3.s[2]\n"
+      "fmla z29.s, z2.s, z3.s[3]\n"
+      "fmla z9.s, z1.s, z4.s[0]\n"
+      "fmla z12.s, z1.s, z4.s[1]\n"
+      "fmla z15.s, z1.s, z4.s[2]\n"
+      "fmla z18.s, z1.s, z4.s[3]\n"
+      "fmla z21.s, z1.s, z3.s[0]\n"
+      "fmla z24.s, z1.s, z3.s[1]\n"
+      "fmla z27.s, z1.s, z3.s[2]\n"
+      "fmla z30.s, z1.s, z3.s[3]\n"
+      "fmla z10.s, z0.s, z4.s[0]\n"
+      "fmla z13.s, z0.s, z4.s[1]\n"
+      "fmla z16.s, z0.s, z4.s[2]\n"
+      "fmla z19.s, z0.s, z4.s[3]\n"
+      "fmla z22.s, z0.s, z3.s[0]\n"
+      "fmla z25.s, z0.s, z3.s[1]\n"
+      "fmla z28.s, z0.s, z3.s[2]\n"
+      "fmla z31.s, z0.s, z3.s[3]\n"
       "5:"  // multiply loop done
       "st1w { z8.s }, p0, [%x[Cpanel]]\n"
       "subs x23, x23, #0x1\n"