diff options
| author | Michael Tyler <michael.tyler@arm.com> | 2023-04-12 17:43:17 +0100 |
|---|---|---|
| committer | michael.tyler <michael.tyler@arm.com> | 2023-06-05 15:57:58 +0000 |
| commit | 74921eee924625426429044decefe3673561b174 (patch) | |
| tree | 654da1a95e3d42d6af8ad1ff27bb40d77b1fd8c5 /src/core/NEON/kernels/arm_gemm/kernels/sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL.hpp | |
| parent | df5d9878008be9b60586df97ebfff197abb5195e (diff) | |
| download | ComputeLibrary-74921eee924625426429044decefe3673561b174.tar.gz | |
Update CPU kernel implementations and guard directives
Resolves COMPMID-6023
Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL.hpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL.hpp | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL.hpp b/src/core/NEON/kernels/arm_gemm/kernels/sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL.hpp index be1106da13..ce10ab30e7 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL.hpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,7 +23,7 @@ */ #pragma once -#ifdef __aarch64__ +#ifdef ARM_COMPUTE_ENABLE_SME2 #include <cstdint> #include "../std_transforms_sme.hpp" @@ -32,7 +32,7 @@ namespace arm_gemm { // Implementations -void sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL(const int8_t *const A, const int8_t *const B, int32_t *const C, int ldc, const int M, const int N, const int K, const int32_t *const bias, const Activation act, bool accumulate, int32_t *const accumulator_buffer); +void sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL(const int8_t *const A, const int8_t *const B, int32_t *const C, int ldc, const int M, const int N, const int K, const int32_t *const bias, const Activation, bool accumulate, int32_t *const accumulator_buffer); class cls_sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL { @@ -40,7 +40,7 @@ public: typedef int8_t operand_type; typedef int32_t result_type; - typedef void (*kern_type)(const int8_t *const A, const int8_t *const B, int32_t *const C, int ldc, const int M, const int N, const int K, const int32_t *const bias, const Activation act, bool accumulate, int32_t *const accumulator_buffer); + typedef void (*kern_type)(const int8_t *const A, const int8_t *const B, int32_t *const C, int ldc, const int M, const int N, const int K, const int32_t *const bias, const Activation, bool accumulate, int32_t *const accumulator_buffer); /* Kernel blocking parameters */ static unsigned int out_height() @@ -83,12 +83,11 @@ public: StdTransformsSME<operand_type, result_type, 4, 1, 4> transforms = {}; - cls_sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL(const CPUInfo *ci) + cls_sme2_interleaved_nomerge_s8s32_mopa_4VLx1VL(const CPUInfo *) { - ARM_COMPUTE_UNUSED(ci); } }; } // namespace arm_gemm -#endif // __aarch64__ +#endif // ARM_COMPUTE_ENABLE_SME2 |