Update CPU kernel implementations and guard directives

Resolves COMPMID-6023

Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>

1 files changed, 63 insertions, 63 deletions

diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp
index a73792036a..b91ae8a948 100644
--- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp
+++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp
@@ -159,101 +159,101 @@ void interleave_block<8, 1, VLType::None, true>(
       "5:"  // Main loop skip
       "cbz %x[width], 10f\n"
       "tbz %x[width], #2, 7f\n"
-      "ldr d31, [x28], #0x8\n"
-      "ldr d30, [x27], #0x8\n"
-      "ldr d29, [x26], #0x8\n"
-      "ldr d28, [x25], #0x8\n"
-      "ldr d27, [x24], #0x8\n"
-      "ldr d26, [x23], #0x8\n"
+      "ldr d30, [x28], #0x8\n"
+      "ldr d29, [x27], #0x8\n"
+      "ldr d28, [x26], #0x8\n"
+      "ldr d27, [x25], #0x8\n"
+      "ldr d26, [x24], #0x8\n"
+      "ldr d25, [x23], #0x8\n"
       "ldr d24, [x22], #0x8\n"
       "ldr d23, [x21], #0x8\n"
       "tbz %x[width], #1, 6f\n"
-      "ld1 { v31.s }[2], [x28], #0x4\n"
-      "ld1 { v30.s }[2], [x27], #0x4\n"
+      "ld1 { v30.s }[2], [x28], #0x4\n"
+      "ld1 { v29.s }[2], [x27], #0x4\n"
       "mov x20, #0x6\n"
-      "ld1 { v29.s }[2], [x26], #0x4\n"
-      "ld1 { v28.s }[2], [x25], #0x4\n"
-      "ld1 { v27.s }[2], [x24], #0x4\n"
-      "ld1 { v26.s }[2], [x23], #0x4\n"
+      "ld1 { v28.s }[2], [x26], #0x4\n"
+      "ld1 { v27.s }[2], [x25], #0x4\n"
+      "ld1 { v26.s }[2], [x24], #0x4\n"
+      "ld1 { v25.s }[2], [x23], #0x4\n"
       "ld1 { v24.s }[2], [x22], #0x4\n"
       "ld1 { v23.s }[2], [x21], #0x4\n"
       "tbz %x[width], #0, 9f\n"
-      "ld1 { v31.h }[6], [x28]\n"
-      "ld1 { v30.h }[6], [x27]\n"
+      "ld1 { v30.h }[6], [x28]\n"
+      "ld1 { v29.h }[6], [x27]\n"
       "mov x20, #0x7\n"
-      "ld1 { v29.h }[6], [x26]\n"
-      "ld1 { v28.h }[6], [x25]\n"
-      "ld1 { v27.h }[6], [x24]\n"
-      "ld1 { v26.h }[6], [x23]\n"
+      "ld1 { v28.h }[6], [x26]\n"
+      "ld1 { v27.h }[6], [x25]\n"
+      "ld1 { v26.h }[6], [x24]\n"
+      "ld1 { v25.h }[6], [x23]\n"
       "ld1 { v24.h }[6], [x22]\n"
       "ld1 { v23.h }[6], [x21]\n"
       "b 9f\n"
       "6:"  // odd_loads_1_4
       "mov x20, #0x4\n"
       "tbz %x[width], #0, 9f\n"
-      "ld1 { v31.h }[4], [x28]\n"
-      "ld1 { v30.h }[4], [x27]\n"
+      "ld1 { v30.h }[4], [x28]\n"
+      "ld1 { v29.h }[4], [x27]\n"
       "mov x20, #0x5\n"
-      "ld1 { v29.h }[4], [x26]\n"
-      "ld1 { v28.h }[4], [x25]\n"
-      "ld1 { v27.h }[4], [x24]\n"
-      "ld1 { v26.h }[4], [x23]\n"
+      "ld1 { v28.h }[4], [x26]\n"
+      "ld1 { v27.h }[4], [x25]\n"
+      "ld1 { v26.h }[4], [x24]\n"
+      "ld1 { v25.h }[4], [x23]\n"
       "ld1 { v24.h }[4], [x22]\n"
       "ld1 { v23.h }[4], [x21]\n"
       "b 9f\n"
       "7:"  // odd_loads_2_0
       "tbz %x[width], #1, 8f\n"
-      "ldr s31, [x28], #0x4\n"
-      "ldr s30, [x27], #0x4\n"
+      "ldr s30, [x28], #0x4\n"
+      "ldr s29, [x27], #0x4\n"
       "mov x20, #0x2\n"
-      "ldr s29, [x26], #0x4\n"
-      "ldr s28, [x25], #0x4\n"
-      "ldr s27, [x24], #0x4\n"
-      "ldr s26, [x23], #0x4\n"
+      "ldr s28, [x26], #0x4\n"
+      "ldr s27, [x25], #0x4\n"
+      "ldr s26, [x24], #0x4\n"
+      "ldr s25, [x23], #0x4\n"
       "ldr s24, [x22], #0x4\n"
       "ldr s23, [x21], #0x4\n"
       "tbz %x[width], #0, 9f\n"
-      "ld1 { v31.h }[2], [x28]\n"
-      "ld1 { v30.h }[2], [x27]\n"
+      "ld1 { v30.h }[2], [x28]\n"
+      "ld1 { v29.h }[2], [x27]\n"
       "mov x20, #0x3\n"
-      "ld1 { v29.h }[2], [x26]\n"
-      "ld1 { v28.h }[2], [x25]\n"
-      "ld1 { v27.h }[2], [x24]\n"
-      "ld1 { v26.h }[2], [x23]\n"
+      "ld1 { v28.h }[2], [x26]\n"
+      "ld1 { v27.h }[2], [x25]\n"
+      "ld1 { v26.h }[2], [x24]\n"
+      "ld1 { v25.h }[2], [x23]\n"
       "ld1 { v24.h }[2], [x22]\n"
       "ld1 { v23.h }[2], [x21]\n"
       "b 9f\n"
       "8:"  // odd_loads_1_0
-      "ldr h31, [x28, #0x0]\n"
-      "ldr h30, [x27, #0x0]\n"
+      "ldr h30, [x28, #0x0]\n"
+      "ldr h29, [x27, #0x0]\n"
       "mov x20, #0x1\n"
-      "ldr h29, [x26, #0x0]\n"
-      "ldr h28, [x25, #0x0]\n"
-      "ldr h27, [x24, #0x0]\n"
-      "ldr h26, [x23, #0x0]\n"
+      "ldr h28, [x26, #0x0]\n"
+      "ldr h27, [x25, #0x0]\n"
+      "ldr h26, [x24, #0x0]\n"
+      "ldr h25, [x23, #0x0]\n"
       "ldr h24, [x22, #0x0]\n"
       "ldr h23, [x21, #0x0]\n"
       "9:"  // Odd load end
-      "zip1 v25.8h, v31.8h, v27.8h\n"
-      "zip1 v18.8h, v29.8h, v24.8h\n"
-      "subs x20, x20, #0x1\n"
       "zip1 v22.8h, v30.8h, v26.8h\n"
-      "zip1 v21.8h, v28.8h, v23.8h\n"
-      "zip1 v17.8h, v25.8h, v18.8h\n"
-      "zip1 v16.8h, v22.8h, v21.8h\n"
-      "zip1 v20.8h, v17.8h, v16.8h\n"
-      "str q20, [%x[out_ptr], #0x0]\n"
-      "add v2.8h, v2.8h, v20.8h\n"
+      "zip1 v21.8h, v28.8h, v24.8h\n"
+      "subs x20, x20, #0x1\n"
+      "zip1 v20.8h, v29.8h, v25.8h\n"
+      "zip1 v19.8h, v27.8h, v23.8h\n"
+      "zip1 v18.8h, v22.8h, v21.8h\n"
+      "zip1 v17.8h, v20.8h, v19.8h\n"
+      "zip1 v16.8h, v18.8h, v17.8h\n"
+      "str q16, [%x[out_ptr], #0x0]\n"
+      "add v2.8h, v2.8h, v16.8h\n"
       "add %x[out_ptr], %x[out_ptr], #0x10\n"
       "beq 10f\n"
-      "zip2 v19.8h, v17.8h, v16.8h\n"
+      "zip2 v16.8h, v18.8h, v17.8h\n"
       "subs x20, x20, #0x1\n"
-      "str q19, [%x[out_ptr], #0x0]\n"
-      "add v2.8h, v2.8h, v19.8h\n"
+      "str q16, [%x[out_ptr], #0x0]\n"
+      "add v2.8h, v2.8h, v16.8h\n"
       "add %x[out_ptr], %x[out_ptr], #0x10\n"
       "beq 10f\n"
-      "zip2 v18.8h, v25.8h, v18.8h\n"
-      "zip2 v17.8h, v22.8h, v21.8h\n"
+      "zip2 v18.8h, v22.8h, v21.8h\n"
+      "zip2 v17.8h, v20.8h, v19.8h\n"
       "subs x20, x20, #0x1\n"
       "zip1 v16.8h, v18.8h, v17.8h\n"
       "str q16, [%x[out_ptr], #0x0]\n"
@@ -266,11 +266,11 @@ void interleave_block<8, 1, VLType::None, true>(
       "add v2.8h, v2.8h, v16.8h\n"
       "add %x[out_ptr], %x[out_ptr], #0x10\n"
       "beq 10f\n"
-      "zip2 v22.8h, v31.8h, v27.8h\n"
-      "zip2 v21.8h, v29.8h, v24.8h\n"
+      "zip2 v22.8h, v30.8h, v26.8h\n"
+      "zip2 v21.8h, v28.8h, v24.8h\n"
       "subs x20, x20, #0x1\n"
-      "zip2 v20.8h, v30.8h, v26.8h\n"
-      "zip2 v19.8h, v28.8h, v23.8h\n"
+      "zip2 v20.8h, v29.8h, v25.8h\n"
+      "zip2 v19.8h, v27.8h, v23.8h\n"
       "zip1 v18.8h, v22.8h, v21.8h\n"
       "zip1 v17.8h, v20.8h, v19.8h\n"
       "zip1 v16.8h, v18.8h, v17.8h\n"
@@ -284,9 +284,9 @@ void interleave_block<8, 1, VLType::None, true>(
       "add v2.8h, v2.8h, v16.8h\n"
       "add %x[out_ptr], %x[out_ptr], #0x10\n"
       "beq 10f\n"
-      "zip2 v18.8h, v22.8h, v21.8h\n"
-      "zip2 v17.8h, v20.8h, v19.8h\n"
-      "zip1 v16.8h, v18.8h, v17.8h\n"
+      "zip2 v17.8h, v22.8h, v21.8h\n"
+      "zip2 v16.8h, v20.8h, v19.8h\n"
+      "zip1 v16.8h, v17.8h, v16.8h\n"
       "str q16, [%x[out_ptr], #0x0]\n"
       "add v2.8h, v2.8h, v16.8h\n"
       "add %x[out_ptr], %x[out_ptr], #0x10\n"