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| author | Michael Tyler <michael.tyler@arm.com> | 2024-06-04 15:47:37 +0100 |
|---|---|---|
| committer | Michael Tyler <michael.tyler@arm.com> | 2024-06-25 09:10:13 +0000 |
| commit | fc94f4d23abd4bc427b701f54ad85282e9ec7872 (patch) | |
| tree | 5e2980599256e2b2f4374e5beb61596fc95c9d5a /src/core/NEON/kernels/arm_conv/pooling/pooling_depthfirst_generic.hpp | |
| parent | c2237ec4094c7824f8f7e61bc89504d01c5b59ff (diff) | |
| download | ComputeLibrary-fc94f4d23abd4bc427b701f54ad85282e9ec7872.tar.gz | |
Update CPU kernels and add mixed sign GEMM support
- Add support for mixed sign quantized convolution.
- Add support for mixed sign dequantized GEMM.
- Add SME FP16 GEMV kernel.
- Change SME vector length function to use RDSVL instead of static variable.
- Add GEMM dilation support internally (not exposed yet).
- Remove unused "get_default_activation_values" functions.
- Add SVE fixed format interleaved BF16 DOT kernel.
- Updates and optimizations to assembly kernels.
Resolves COMPMID-6926
Change-Id: I227f502502611d4cc4111c89e30c53ce94079544
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/11570
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/pooling_depthfirst_generic.hpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/pooling/pooling_depthfirst_generic.hpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/pooling_depthfirst_generic.hpp b/src/core/NEON/kernels/arm_conv/pooling/pooling_depthfirst_generic.hpp index ded2c75127..cb241cf76f 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/pooling_depthfirst_generic.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/pooling_depthfirst_generic.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -136,8 +136,8 @@ class PoolingDepthfirstGeneric : public DepthfirstDriver<TInput, TOutput> const OutputStage m_os; protected: - size_t get_working_size_per_thread() const override { return 0; } - void initialise_working_space(void *) const override { /* Nothing */ } + size_t get_working_size_per_thread(unsigned int) const override { return 0; } + void initialise_working_space(void *, unsigned int) const override { /* Nothing */ } /* Compute a portion of the output tensor with padding. */ void compute_tile_padded( |