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author | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-02-02 14:59:09 +0000 |
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committer | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-02-04 17:43:55 +0000 |
commit | cf87f509fc23d02c56569f794a3fb59e1b8be277 (patch) | |
tree | 0fe55158f2065dc6a314e82935558b9748165285 /src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst | |
parent | 89de118ccbebd5a943634137d0c160d4867da49c (diff) | |
download | ComputeLibrary-cf87f509fc23d02c56569f794a3fb59e1b8be277.tar.gz |
Tweak scheduling use of SQDMULH in quantized AVG pooling
Resolves COMPMID-4195
Change-Id: Ie5116c1ddddccafba40432fd4b5245bb27890a88
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4997
Reviewed-by: TeresaARM <teresa.charlinreyes@arm.com>
Reviewed-by: Manuel Bottini <manuel.bottini@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst')
-rw-r--r-- | src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 9ad4a39a83..ea7e2195d1 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -63,23 +63,24 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( __asm__ __volatile__( "ldr x15, [%x[args], %[offsetof_n_channels]]\n" "mov x14, #0x0\n" - "ldr x19, [%x[args], %[offsetof_outptrs]]\n" + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" "mov x13, #0x0\n" - "ldp x12, x11, [x19, #0x0]\n" - "cmp x15, #0x4\n" - "ldp x10, x9, [x19, #0x10]\n" "ldr x19, [%x[args], %[offsetof_inptrs]]\n" + "cmp x15, #0x4\n" + "ldp x12, x11, [x20, #0x0]\n" + "ldp x10, x9, [x20, #0x10]\n" "ldp x28, x27, [x19, #0x0]\n" "ldp x26, x25, [x19, #0x10]\n" "ldp x24, x23, [x19, #0x20]\n" "ldp x22, x21, [x19, #0x30]\n" "ldr x20, [x19, #0x40]\n" "blt 3f\n" - "lsr x19, x15, #0x2\n" - "sub x15, x15, x19, LSL #2\n" "ldr q30, [x27, x14]\n" + "lsr x19, x15, #0x2\n" "ldr q29, [x24, x14]\n" + "sub x15, x15, x19, LSL #2\n" "ldr q28, [x21, x14]\n" + "subs x19, x19, #0x1\n" "ldr q27, [x25, x14]\n" "ldr q26, [x28, x14]\n" "ldr q25, [x23, x14]\n" @@ -87,11 +88,11 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr q23, [x22, x14]\n" "ldr q22, [x20, x14]\n" "add x14, x14, #0x10\n" - "subs x19, x19, #0x1\n" "beq 2f\n" "1:" // Vector: Loop "fmax v21.4s, v30.4s, v29.4s\n" "ldr q30, [x27, x14]\n" + "subs x19, x19, #0x1\n" "fmax v20.4s, v29.4s, v28.4s\n" "ldr q29, [x24, x14]\n" "fmax v19.4s, v27.4s, v26.4s\n" @@ -108,14 +109,13 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr q23, [x22, x14]\n" "fmax v17.4s, v20.4s, v17.4s\n" "ldr q22, [x20, x14]\n" - "fmax v16.4s, v20.4s, v16.4s\n" "add x14, x14, #0x10\n" + "fmax v16.4s, v20.4s, v16.4s\n" "str q19, [x12, x13]\n" "str q18, [x11, x13]\n" "str q17, [x10, x13]\n" "str q16, [x9, x13]\n" "add x13, x13, #0x10\n" - "subs x19, x19, #0x1\n" "bgt 1b\n" "2:" // Vector: Tail "fmax v21.4s, v30.4s, v29.4s\n" @@ -136,6 +136,7 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "cbz x15, 4f\n" "3:" // Oddments "ldr s30, [x27, x14]\n" + "subs x15, x15, #0x1\n" "ldr s29, [x24, x14]\n" "fmax v21.4s, v30.4s, v29.4s\n" "ldr s28, [x21, x14]\n" @@ -150,9 +151,8 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr s22, [x20, x14]\n" "add x14, x14, #0x4\n" "fmax v18.4s, v25.4s, v24.4s\n" - "subs x15, x15, #0x1\n" - "fmax v17.4s, v23.4s, v27.4s\n" "str s19, [x12, x13]\n" + "fmax v17.4s, v23.4s, v27.4s\n" "fmax v16.4s, v25.4s, v22.4s\n" "fmax v18.4s, v21.4s, v18.4s\n" "str s18, [x11, x13]\n" |