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| author | Michael Tyler <michael.tyler@arm.com> | 2023-04-12 17:43:17 +0100 |
|---|---|---|
| committer | michael.tyler <michael.tyler@arm.com> | 2023-06-05 15:57:58 +0000 |
| commit | 74921eee924625426429044decefe3673561b174 (patch) | |
| tree | 654da1a95e3d42d6af8ad1ff27bb40d77b1fd8c5 /src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_generic_output9_mla_depthfirst | |
| parent | df5d9878008be9b60586df97ebfff197abb5195e (diff) | |
| download | ComputeLibrary-74921eee924625426429044decefe3673561b174.tar.gz | |
Update CPU kernel implementations and guard directives
Resolves COMPMID-6023
Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_generic_output9_mla_depthfirst')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp index 204f36edca..d53daaa8a0 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp @@ -55,9 +55,9 @@ void sve_fp32_nhwc_generic_output9_mla_depthfirst_impl( "ld1w { z23.s }, p0/Z, [%x[bias], x11, LSL #2]\n" "2:" // Channel loop: Load bias: Done "mov x10, %x[inptrs]\n" - "ldp x9, x28, [x10], #0x10\n" - "ldp x27, x26, [x10], #0x10\n" - "subs x25, %x[n_points], #0x1\n" + "ldp x28, x27, [x10], #0x10\n" + "ldp x26, x25, [x10], #0x10\n" + "subs x9, %x[n_points], #0x1\n" "ldp x24, x23, [x10], #0x10\n" "ldp x22, x21, [x10], #0x10\n" "mov z24.d, z23.d\n" @@ -68,12 +68,12 @@ void sve_fp32_nhwc_generic_output9_mla_depthfirst_impl( "ld1w { z0.s }, p1/Z, [%x[params]]\n" "mov z28.d, z23.d\n" "mov z29.d, z23.d\n" - "ld1w { z14.s }, p0/Z, [x9, x11, LSL #2]\n" - "ld1w { z15.s }, p0/Z, [x28, x11, LSL #2]\n" + "ld1w { z14.s }, p0/Z, [x28, x11, LSL #2]\n" + "ld1w { z15.s }, p0/Z, [x27, x11, LSL #2]\n" "mov z30.d, z23.d\n" "mov z31.d, z23.d\n" - "ld1w { z16.s }, p0/Z, [x27, x11, LSL #2]\n" - "ld1w { z17.s }, p0/Z, [x26, x11, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x26, x11, LSL #2]\n" + "ld1w { z17.s }, p0/Z, [x25, x11, LSL #2]\n" "ld1w { z18.s }, p0/Z, [x24, x11, LSL #2]\n" "ld1w { z19.s }, p0/Z, [x23, x11, LSL #2]\n" "addvl %x[params], %x[params], #1\n" @@ -82,9 +82,9 @@ void sve_fp32_nhwc_generic_output9_mla_depthfirst_impl( "ld1w { z22.s }, p0/Z, [x20, x11, LSL #2]\n" "ble 4f\n" "3:" // Channel loop: Planar loop - "ldp x9, x28, [x10], #0x10\n" - "ldp x27, x26, [x10], #0x10\n" - "subs x25, x25, #0x1\n" + "ldp x28, x27, [x10], #0x10\n" + "ldp x26, x25, [x10], #0x10\n" + "subs x9, x9, #0x1\n" "fmla z23.s, p1/M, z14.s, z0.s\n" "ldp x24, x23, [x10], #0x10\n" "ldp x22, x21, [x10], #0x10\n" @@ -93,15 +93,15 @@ void sve_fp32_nhwc_generic_output9_mla_depthfirst_impl( "ldr x20, [x10], #0x8\n" "fmla z26.s, p1/M, z17.s, z0.s\n" "fmla z27.s, p1/M, z18.s, z0.s\n" - "ld1w { z14.s }, p0/Z, [x9, x11, LSL #2]\n" + "ld1w { z14.s }, p0/Z, [x28, x11, LSL #2]\n" "fmla z28.s, p1/M, z19.s, z0.s\n" "fmla z29.s, p1/M, z20.s, z0.s\n" - "ld1w { z15.s }, p0/Z, [x28, x11, LSL #2]\n" - "ld1w { z16.s }, p0/Z, [x27, x11, LSL #2]\n" + "ld1w { z15.s }, p0/Z, [x27, x11, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x26, x11, LSL #2]\n" "fmla z30.s, p1/M, z21.s, z0.s\n" "fmla z31.s, p1/M, z22.s, z0.s\n" "ld1w { z0.s }, p1/Z, [%x[params]]\n" - "ld1w { z17.s }, p0/Z, [x26, x11, LSL #2]\n" + "ld1w { z17.s }, p0/Z, [x25, x11, LSL #2]\n" "ld1w { z18.s }, p0/Z, [x24, x11, LSL #2]\n" "ld1w { z19.s }, p0/Z, [x23, x11, LSL #2]\n" "addvl %x[params], %x[params], #1\n" |