diff options
author | Michael Tyler <michael.tyler@arm.com> | 2023-04-12 17:43:17 +0100 |
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committer | michael.tyler <michael.tyler@arm.com> | 2023-06-05 15:57:58 +0000 |
commit | 74921eee924625426429044decefe3673561b174 (patch) | |
tree | 654da1a95e3d42d6af8ad1ff27bb40d77b1fd8c5 /src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp | |
parent | df5d9878008be9b60586df97ebfff197abb5195e (diff) | |
download | ComputeLibrary-74921eee924625426429044decefe3673561b174.tar.gz |
Update CPU kernel implementations and guard directives
Resolves COMPMID-6023
Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp')
-rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp | 252 |
1 files changed, 126 insertions, 126 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp index a570c5aa6a..1bdef85274 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp @@ -25,7 +25,7 @@ #include <cstddef> #include <cstdint> -#if __aarch64__ && defined(ARM_COMPUTE_ENABLE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace depthwise { @@ -108,10 +108,10 @@ void sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl( "whilelt p2.s, XZR, %x[n_channels]\n" "madd x20, x14, x12, x20\n" // offset += tile_j * ld_output_col "ldr x28, [%x[params_struct], %[offsetof_args_outptr]]\n" - "ld1w { z18.s }, p3/Z, [x10]\n" + "ld1w { z27.s }, p3/Z, [x10]\n" "add x27, x13, x13\n" "mul x21, x21, x25\n" // offset *= kernel_stride * output_size - "add x9, x9, x21, LSL #2\n" // inptr[0] += offset * sizeof(float) + "add x9, x9, x21, LSL #2\n" // inptr[0] += offset * sizeof(float) "ld1w { z0.s }, p3/Z, [x10, #1, MUL VL]\n" "ld1w { z1.s }, p3/Z, [x10, #2, MUL VL]\n" "mul x20, x20, x24\n" // offset *= output_tile_size @@ -125,10 +125,10 @@ void sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl( "ld1w { z6.s }, p3/Z, [x10, #7, MUL VL]\n" "addvl x10, x10, #16\n" "add x28, x28, x20, LSL #2\n" // outptrs[0] += offset * sizeof(float) - "ld1rw { z17.s }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "ld1rw { z26.s }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" "cmp x11, %x[n_channels]\n" "add x23, x25, x23, LSL #2\n" - "ld1rw { z16.s }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "ld1rw { z25.s }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" "ld1w { z7.s }, p3/Z, [x10, #-8, MUL VL]\n" "add x22, x28, x22, LSL #2\n" "mov x21, #0x0\n" @@ -142,175 +142,175 @@ void sve_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl( "ld1w { z13.s }, p2/Z, [x25, x13, LSL #2]\n" "bge 3f\n" "2:" // Tile loop: Channel loop - "movprfx z28, z18\n fmla z28.s, p3/M, z4.s, z9.s\n" - "movprfx z29, z18\n fmla z29.s, p3/M, z3.s, z9.s\n" + "movprfx z24, z27\n fmla z24.s, p3/M, z4.s, z9.s\n" + "movprfx z23, z27\n fmla z23.s, p3/M, z3.s, z9.s\n" "whilelt p1.s, x11, %x[n_channels]\n" "incw x21\n" - "movprfx z30, z18\n fmla z30.s, p3/M, z1.s, z9.s\n" - "movprfx z31, z18\n fmla z31.s, p3/M, z0.s, z9.s\n" - "ld1w { z9.s }, p2/Z, [x23]\n" + "movprfx z22, z27\n fmla z22.s, p3/M, z1.s, z9.s\n" + "movprfx z21, z27\n fmla z21.s, p3/M, z0.s, z9.s\n" + "ld1w { z18.s }, p2/Z, [x23]\n" "incw x11\n" - "fmla z28.s, p3/M, z0.s, z10.s\n" - "fmla z29.s, p3/M, z2.s, z11.s\n" - "ld1w { z11.s }, p2/Z, [x23, x24, LSL #2]\n" - "ld1w { z10.s }, p2/Z, [x25, x27, LSL #2]\n" - "fmla z30.s, p3/M, z2.s, z12.s\n" - "fmla z31.s, p3/M, z1.s, z12.s\n" + "fmla z24.s, p3/M, z0.s, z10.s\n" + "fmla z23.s, p3/M, z2.s, z11.s\n" + "ld1w { z17.s }, p2/Z, [x23, x24, LSL #2]\n" + "ld1w { z20.s }, p2/Z, [x25, x27, LSL #2]\n" + "fmla z22.s, p3/M, z2.s, z12.s\n" + "fmla z21.s, p3/M, z1.s, z12.s\n" "mov p0.b, p2.b\n" - "ld1w { z18.s }, p3/Z, [x10]\n" - "fmla z28.s, p3/M, z5.s, z12.s\n" - "fmla z29.s, p3/M, z4.s, z12.s\n" - "ld1w { z12.s }, p2/Z, [x9, x13, LSL #2]\n" + "ld1w { z27.s }, p3/Z, [x10]\n" + "fmla z24.s, p3/M, z5.s, z12.s\n" + "fmla z23.s, p3/M, z4.s, z12.s\n" + "ld1w { z16.s }, p2/Z, [x9, x13, LSL #2]\n" "incw x20\n" - "fmla z30.s, p3/M, z6.s, z9.s\n" - "fmla z31.s, p3/M, z3.s, z13.s\n" - "ld1w { z9.s }, p2/Z, [x9, x27, LSL #2]\n" + "fmla z22.s, p3/M, z6.s, z18.s\n" + "fmla z21.s, p3/M, z3.s, z13.s\n" + "ld1w { z18.s }, p2/Z, [x9, x27, LSL #2]\n" "addvl x9, x9, #1\n" - "fmla z28.s, p3/M, z7.s, z13.s\n" - "fmla z29.s, p3/M, z6.s, z13.s\n" - "fmla z30.s, p3/M, z4.s, z13.s\n" - "fmla z31.s, p3/M, z8.s, z11.s\n" - "ld1w { z11.s }, p2/Z, [x26]\n" - "fmla z28.s, p3/M, z1.s, z12.s\n" - "fmla z29.s, p3/M, z0.s, z12.s\n" - "ld1w { z12.s }, p2/Z, [x26, x24, LSL #2]\n" + "fmla z24.s, p3/M, z7.s, z13.s\n" + "fmla z23.s, p3/M, z6.s, z13.s\n" + "fmla z22.s, p3/M, z4.s, z13.s\n" + "fmla z21.s, p3/M, z8.s, z17.s\n" + "ld1w { z17.s }, p2/Z, [x26]\n" + "fmla z24.s, p3/M, z1.s, z16.s\n" + "fmla z23.s, p3/M, z0.s, z16.s\n" + "ld1w { z16.s }, p2/Z, [x26, x24, LSL #2]\n" "addvl x26, x26, #1\n" - "fmla z30.s, p3/M, z5.s, z10.s\n" - "fmla z31.s, p3/M, z4.s, z10.s\n" + "fmla z22.s, p3/M, z5.s, z20.s\n" + "fmla z21.s, p3/M, z4.s, z20.s\n" "ld1w { z4.s }, p3/Z, [x10, #5, MUL VL]\n" - "fmla z28.s, p3/M, z2.s, z9.s\n" - "fmla z29.s, p3/M, z1.s, z9.s\n" - "ld1w { z9.s }, p2/Z, [x25]\n" + "fmla z24.s, p3/M, z2.s, z18.s\n" + "fmla z23.s, p3/M, z1.s, z18.s\n" + "ld1w { z19.s }, p2/Z, [x25]\n" "ld1w { z1.s }, p3/Z, [x10, #2, MUL VL]\n" - "fmla z30.s, p3/M, z0.s, z11.s\n" - "fmla z31.s, p3/M, z2.s, z12.s\n" + "fmla z22.s, p3/M, z0.s, z17.s\n" + "fmla z21.s, p3/M, z2.s, z16.s\n" "ld1w { z0.s }, p3/Z, [x10, #1, MUL VL]\n" "ld1w { z2.s }, p3/Z, [x10, #3, MUL VL]\n" - "fmla z28.s, p3/M, z8.s, z10.s\n" - "fmla z29.s, p3/M, z7.s, z10.s\n" - "ld1w { z10.s }, p2/Z, [x25, x24, LSL #2]\n" + "fmla z24.s, p3/M, z8.s, z20.s\n" + "fmla z23.s, p3/M, z7.s, z20.s\n" + "ld1w { z18.s }, p2/Z, [x25, x24, LSL #2]\n" "addvl x25, x25, #1\n" - "fmla z30.s, p3/M, z3.s, z9.s\n" - "fmla z31.s, p3/M, z5.s, z10.s\n" + "fmla z22.s, p3/M, z3.s, z19.s\n" + "fmla z21.s, p3/M, z5.s, z18.s\n" "ld1w { z13.s }, p1/Z, [x25, x13, LSL #2]\n" - "fmla z28.s, p3/M, z3.s, z11.s\n" - "ld1w { z11.s }, p2/Z, [x23, x13, LSL #2]\n" - "fmla z29.s, p3/M, z5.s, z12.s\n" - "ld1w { z12.s }, p2/Z, [x23, x27, LSL #2]\n" - "fmla z30.s, p3/M, z7.s, z11.s\n" - "fmla z31.s, p3/M, z6.s, z11.s\n" + "fmla z24.s, p3/M, z3.s, z17.s\n" + "ld1w { z17.s }, p2/Z, [x23, x13, LSL #2]\n" + "fmla z23.s, p3/M, z5.s, z16.s\n" + "ld1w { z16.s }, p2/Z, [x23, x27, LSL #2]\n" + "fmla z22.s, p3/M, z7.s, z17.s\n" + "fmla z21.s, p3/M, z6.s, z17.s\n" "ld1w { z3.s }, p3/Z, [x10, #4, MUL VL]\n" "ld1w { z5.s }, p3/Z, [x10, #6, MUL VL]\n" - "fmla z28.s, p3/M, z6.s, z9.s\n" - "fmla z29.s, p3/M, z8.s, z10.s\n" - "fmax z28.s, p3/M, z28.s, z17.s\n" - "fmax z29.s, p3/M, z29.s, z17.s\n" - "fmla z30.s, p3/M, z8.s, z12.s\n" - "fmla z31.s, p3/M, z7.s, z12.s\n" - "fmax z30.s, p3/M, z30.s, z17.s\n" - "fmax z31.s, p3/M, z31.s, z17.s\n" + "fmla z24.s, p3/M, z6.s, z19.s\n" + "fmla z23.s, p3/M, z8.s, z18.s\n" + "fmax z24.s, p3/M, z24.s, z26.s\n" + "fmax z23.s, p3/M, z23.s, z26.s\n" + "fmla z22.s, p3/M, z8.s, z16.s\n" + "fmla z21.s, p3/M, z7.s, z16.s\n" + "fmax z22.s, p3/M, z22.s, z26.s\n" + "fmax z21.s, p3/M, z21.s, z26.s\n" "ld1w { z6.s }, p3/Z, [x10, #7, MUL VL]\n" "addvl x10, x10, #16\n" "whilelt p2.s, x21, %x[n_channels]\n" "ld1w { z9.s }, p1/Z, [x26, x13, LSL #2]\n" "cmp x11, %x[n_channels]\n" - "fmin z28.s, p3/M, z28.s, z16.s\n" + "fmin z24.s, p3/M, z24.s, z25.s\n" "ld1w { z10.s }, p1/Z, [x9]\n" "ld1w { z11.s }, p1/Z, [x9, x24, LSL #2]\n" - "fmin z29.s, p3/M, z29.s, z16.s\n" - "fmin z30.s, p3/M, z30.s, z16.s\n" + "fmin z23.s, p3/M, z23.s, z25.s\n" + "fmin z22.s, p3/M, z22.s, z25.s\n" "ld1w { z12.s }, p1/Z, [x26, x27, LSL #2]\n" - "st1w { z28.s }, p0, [x28]\n" - "fmin z31.s, p3/M, z31.s, z16.s\n" + "st1w { z24.s }, p0, [x28]\n" + "fmin z21.s, p3/M, z21.s, z25.s\n" "addvl x23, x23, #1\n" - "st1w { z29.s }, p0, [x28, x12, LSL #2]\n" + "st1w { z23.s }, p0, [x28, x12, LSL #2]\n" "ld1w { z7.s }, p3/Z, [x10, #-8, MUL VL]\n" - "st1w { z30.s }, p0, [x22]\n" + "st1w { z22.s }, p0, [x22]\n" "addvl x28, x28, #1\n" "ld1w { z8.s }, p3/Z, [x10, #-7, MUL VL]\n" "addvl x10, x10, #-6\n" - "st1w { z31.s }, p0, [x22, x12, LSL #2]\n" + "st1w { z21.s }, p0, [x22, x12, LSL #2]\n" "addvl x22, x22, #1\n" "blt 2b\n" "3:" // Tile loop: Channel tail - "movprfx z28, z18\n fmla z28.s, p3/M, z4.s, z9.s\n" - "movprfx z29, z18\n fmla z29.s, p3/M, z3.s, z9.s\n" + "movprfx z24, z27\n fmla z24.s, p3/M, z4.s, z9.s\n" + "movprfx z23, z27\n fmla z23.s, p3/M, z3.s, z9.s\n" "ldr x14, [%x[params_struct], %[offsetof_args_tile_j]]\n" "ldr x10, [%x[params_struct], %[offsetof_args_tile_i]]\n" - "movprfx z30, z18\n fmla z30.s, p3/M, z1.s, z9.s\n" - "movprfx z31, z18\n fmla z31.s, p3/M, z0.s, z9.s\n" - "ld1w { z9.s }, p2/Z, [x23]\n" + "movprfx z22, z27\n fmla z22.s, p3/M, z1.s, z9.s\n" + "movprfx z21, z27\n fmla z21.s, p3/M, z0.s, z9.s\n" + "ld1w { z18.s }, p2/Z, [x23]\n" "ldr x20, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" - "fmla z28.s, p3/M, z0.s, z10.s\n" - "fmla z29.s, p3/M, z2.s, z11.s\n" - "ld1w { z11.s }, p2/Z, [x23, x24, LSL #2]\n" - "ld1w { z10.s }, p2/Z, [x25, x27, LSL #2]\n" - "fmla z30.s, p3/M, z2.s, z12.s\n" - "fmla z31.s, p3/M, z1.s, z12.s\n" + "fmla z24.s, p3/M, z0.s, z10.s\n" + "fmla z23.s, p3/M, z2.s, z11.s\n" + "ld1w { z17.s }, p2/Z, [x23, x24, LSL #2]\n" + "ld1w { z20.s }, p2/Z, [x25, x27, LSL #2]\n" + "fmla z22.s, p3/M, z2.s, z12.s\n" + "fmla z21.s, p3/M, z1.s, z12.s\n" "add x14, x14, #0x1\n" "cmp x14, x20\n" - "fmla z28.s, p3/M, z5.s, z12.s\n" - "fmla z29.s, p3/M, z4.s, z12.s\n" - "ld1w { z12.s }, p2/Z, [x9, x13, LSL #2]\n" + "fmla z24.s, p3/M, z5.s, z12.s\n" + "fmla z23.s, p3/M, z4.s, z12.s\n" + "ld1w { z16.s }, p2/Z, [x9, x13, LSL #2]\n" "add x21, x10, #0x1\n" - "fmla z30.s, p3/M, z6.s, z9.s\n" - "fmla z31.s, p3/M, z3.s, z13.s\n" - "ld1w { z9.s }, p2/Z, [x9, x27, LSL #2]\n" + "fmla z22.s, p3/M, z6.s, z18.s\n" + "fmla z21.s, p3/M, z3.s, z13.s\n" + "ld1w { z18.s }, p2/Z, [x9, x27, LSL #2]\n" "ldr x20, [%x[params_struct], %[offsetof_args_n_tile_rows]]\n" - "fmla z28.s, p3/M, z7.s, z13.s\n" - "fmla z29.s, p3/M, z6.s, z13.s\n" + "fmla z24.s, p3/M, z7.s, z13.s\n" + "fmla z23.s, p3/M, z6.s, z13.s\n" "csel x10, x10, x21, LT\n" "mov p0.b, p2.b\n" - "fmla z30.s, p3/M, z4.s, z13.s\n" - "fmla z31.s, p3/M, z8.s, z11.s\n" - "ld1w { z11.s }, p2/Z, [x26]\n" + "fmla z22.s, p3/M, z4.s, z13.s\n" + "fmla z21.s, p3/M, z8.s, z17.s\n" + "ld1w { z17.s }, p2/Z, [x26]\n" "csel x14, x14, XZR, LT\n" - "fmla z28.s, p3/M, z1.s, z12.s\n" - "fmla z29.s, p3/M, z0.s, z12.s\n" - "ld1w { z12.s }, p2/Z, [x26, x24, LSL #2]\n" + "fmla z24.s, p3/M, z1.s, z16.s\n" + "fmla z23.s, p3/M, z0.s, z16.s\n" + "ld1w { z16.s }, p2/Z, [x26, x24, LSL #2]\n" "cmp x10, x20\n" - "fmla z30.s, p3/M, z5.s, z10.s\n" - "fmla z31.s, p3/M, z4.s, z10.s\n" - "fmla z28.s, p3/M, z2.s, z9.s\n" - "fmla z29.s, p3/M, z1.s, z9.s\n" - "ld1w { z9.s }, p2/Z, [x25]\n" - "fmla z30.s, p3/M, z0.s, z11.s\n" - "fmla z31.s, p3/M, z2.s, z12.s\n" - "fmla z28.s, p3/M, z8.s, z10.s\n" - "fmla z29.s, p3/M, z7.s, z10.s\n" - "ld1w { z10.s }, p2/Z, [x25, x24, LSL #2]\n" - "fmla z30.s, p3/M, z3.s, z9.s\n" - "fmla z31.s, p3/M, z5.s, z10.s\n" - "fmla z28.s, p3/M, z3.s, z11.s\n" - "ld1w { z11.s }, p2/Z, [x23, x13, LSL #2]\n" - "fmla z29.s, p3/M, z5.s, z12.s\n" - "ld1w { z12.s }, p2/Z, [x23, x27, LSL #2]\n" - "fmla z30.s, p3/M, z7.s, z11.s\n" - "fmla z31.s, p3/M, z6.s, z11.s\n" - "fmla z28.s, p3/M, z6.s, z9.s\n" - "fmla z29.s, p3/M, z8.s, z10.s\n" - "fmax z28.s, p3/M, z28.s, z17.s\n" - "fmax z29.s, p3/M, z29.s, z17.s\n" - "fmla z30.s, p3/M, z8.s, z12.s\n" - "fmla z31.s, p3/M, z7.s, z12.s\n" - "fmax z30.s, p3/M, z30.s, z17.s\n" - "fmax z31.s, p3/M, z31.s, z17.s\n" - "fmin z28.s, p3/M, z28.s, z16.s\n" - "fmin z29.s, p3/M, z29.s, z16.s\n" - "st1w { z28.s }, p0, [x28]\n" - "fmin z30.s, p3/M, z30.s, z16.s\n" - "fmin z31.s, p3/M, z31.s, z16.s\n" - "st1w { z29.s }, p0, [x28, x12, LSL #2]\n" - "st1w { z30.s }, p0, [x22]\n" - "st1w { z31.s }, p0, [x22, x12, LSL #2]\n" + "fmla z22.s, p3/M, z5.s, z20.s\n" + "fmla z21.s, p3/M, z4.s, z20.s\n" + "fmla z24.s, p3/M, z2.s, z18.s\n" + "fmla z23.s, p3/M, z1.s, z18.s\n" + "ld1w { z19.s }, p2/Z, [x25]\n" + "fmla z22.s, p3/M, z0.s, z17.s\n" + "fmla z21.s, p3/M, z2.s, z16.s\n" + "fmla z24.s, p3/M, z8.s, z20.s\n" + "fmla z23.s, p3/M, z7.s, z20.s\n" + "ld1w { z18.s }, p2/Z, [x25, x24, LSL #2]\n" + "fmla z22.s, p3/M, z3.s, z19.s\n" + "fmla z21.s, p3/M, z5.s, z18.s\n" + "fmla z24.s, p3/M, z3.s, z17.s\n" + "ld1w { z17.s }, p2/Z, [x23, x13, LSL #2]\n" + "fmla z23.s, p3/M, z5.s, z16.s\n" + "ld1w { z16.s }, p2/Z, [x23, x27, LSL #2]\n" + "fmla z22.s, p3/M, z7.s, z17.s\n" + "fmla z21.s, p3/M, z6.s, z17.s\n" + "fmla z24.s, p3/M, z6.s, z19.s\n" + "fmla z23.s, p3/M, z8.s, z18.s\n" + "fmax z24.s, p3/M, z24.s, z26.s\n" + "fmax z23.s, p3/M, z23.s, z26.s\n" + "fmla z22.s, p3/M, z8.s, z16.s\n" + "fmla z21.s, p3/M, z7.s, z16.s\n" + "fmax z22.s, p3/M, z22.s, z26.s\n" + "fmax z21.s, p3/M, z21.s, z26.s\n" + "fmin z24.s, p3/M, z24.s, z25.s\n" + "fmin z23.s, p3/M, z23.s, z25.s\n" + "st1w { z24.s }, p0, [x28]\n" + "fmin z22.s, p3/M, z22.s, z25.s\n" + "fmin z21.s, p3/M, z21.s, z25.s\n" + "st1w { z23.s }, p0, [x28, x12, LSL #2]\n" + "st1w { z22.s }, p0, [x22]\n" + "st1w { z21.s }, p0, [x22, x12, LSL #2]\n" "blt 1b\n" : : [n_channels] "r" ((unsigned long) n_channels), [offsetof_args_inptr] "I" (offsetof(Args, inptr)), [offsetof_args_ld_input_col] "I" (offsetof(Args, ld_input_col)), [offsetof_args_ld_input_row] "I" (offsetof(Args, ld_input_row)), [offsetof_args_ld_output_col] "I" (offsetof(Args, ld_output_col)), [offsetof_args_ld_output_row] "I" (offsetof(Args, ld_output_row)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_n_tile_cols] "I" (offsetof(Args, n_tile_cols)), [offsetof_args_n_tile_rows] "I" (offsetof(Args, n_tile_rows)), [offsetof_args_outptr] "I" (offsetof(Args, outptr)), [offsetof_args_params] "I" (offsetof(Args, params)), [offsetof_args_tile_i] "I" (offsetof(Args, tile_i)), [offsetof_args_tile_j] "I" (offsetof(Args, tile_j)), [params_struct] "r" (¶ms_struct) - : "cc", "memory", "p0", "p1", "p2", "p3", "x9", "x10", "x11", "x12", "x13", "x14", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z16", "z17", "z18", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "x9", "x10", "x11", "x12", "x13", "x14", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27" ); } } // namespace depthwise } // namespace arm_conv -#endif // __aarch64__ && defined(ARM_COMPUTE_ENABLE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) |