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| author | ramelg01 <ramy.elgammal@arm.com> | 2022-05-04 15:12:21 +0100 |
|---|---|---|
| committer | Pablo Marquez Tello <pablo.tello@arm.com> | 2022-05-05 08:54:15 +0000 |
| commit | 638b7e4f6b1125b74f27f90dea2cd23eca52bfe8 (patch) | |
| tree | 68cf88a73c990ad580f200b6ddff76d50860c1ea /src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp | |
| parent | facd9dd4c75feb886240a2b55cefe55ccf773f63 (diff) | |
| download | ComputeLibrary-638b7e4f6b1125b74f27f90dea2cd23eca52bfe8.tar.gz | |
Fix for Neon™ Depthwise Android P VTS test failure
Resolves: COMPMID-5237
Signed-off-by: ramy.elgammal@arm.com
Change-Id: Ib1f5e262030e915a038cef587001708bbaf14c56
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7508
Reviewed-by: David Mansell
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp index 7f1fd1d568..9ac7173b4c 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp @@ -502,24 +502,24 @@ void a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( "smlal2 v6.4s, v24.8h, v3.8h\n" "smlal v11.4s, v28.4h, v4.4h\n" "smlal v14.4s, v26.4h, v4.4h\n" - "sqdmulh v11.4s, v11.4s, v17.4s\n" + "sqrdmulh v11.4s, v11.4s, v17.4s\n" "smlal v9.4s, v24.4h, v4.4h\n" "smlal v7.4s, v27.4h, v4.4h\n" - "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" "smlal2 v21.4s, v28.8h, v4.8h\n" "smlal2 v10.4s, v26.8h, v4.8h\n" - "sqdmulh v9.4s, v9.4s, v17.4s\n" + "sqrdmulh v9.4s, v9.4s, v17.4s\n" "smlal2 v8.4s, v24.8h, v4.8h\n" "smlal2 v6.4s, v27.8h, v4.8h\n" - "sqdmulh v7.4s, v7.4s, v17.4s\n" + "sqrdmulh v7.4s, v7.4s, v17.4s\n" "and v23.16b, v11.16b, v5.16b\n" - "sqdmulh v21.4s, v21.4s, v18.4s\n" + "sqrdmulh v21.4s, v21.4s, v18.4s\n" "and v22.16b, v14.16b, v5.16b\n" - "sqdmulh v10.4s, v10.4s, v18.4s\n" + "sqrdmulh v10.4s, v10.4s, v18.4s\n" "and v17.16b, v9.16b, v5.16b\n" - "sqdmulh v8.4s, v8.4s, v18.4s\n" + "sqrdmulh v8.4s, v8.4s, v18.4s\n" "and v20.16b, v7.16b, v5.16b\n" - "sqdmulh v6.4s, v6.4s, v18.4s\n" + "sqrdmulh v6.4s, v6.4s, v18.4s\n" "sshr v23.4s, v23.4s, #0x1f\n" "and v19.16b, v21.16b, v29.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" @@ -945,24 +945,24 @@ void a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( "smlal2 v6.4s, v24.8h, v3.8h\n" "smlal v11.4s, v28.4h, v4.4h\n" "smlal v14.4s, v26.4h, v4.4h\n" - "sqdmulh v11.4s, v11.4s, v17.4s\n" + "sqrdmulh v11.4s, v11.4s, v17.4s\n" "smlal v9.4s, v24.4h, v4.4h\n" "smlal v7.4s, v27.4h, v4.4h\n" - "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" "smlal2 v21.4s, v28.8h, v4.8h\n" "smlal2 v10.4s, v26.8h, v4.8h\n" - "sqdmulh v9.4s, v9.4s, v17.4s\n" + "sqrdmulh v9.4s, v9.4s, v17.4s\n" "smlal2 v8.4s, v24.8h, v4.8h\n" "smlal2 v6.4s, v27.8h, v4.8h\n" - "sqdmulh v7.4s, v7.4s, v17.4s\n" + "sqrdmulh v7.4s, v7.4s, v17.4s\n" "and v23.16b, v11.16b, v5.16b\n" - "sqdmulh v21.4s, v21.4s, v18.4s\n" + "sqrdmulh v21.4s, v21.4s, v18.4s\n" "and v22.16b, v14.16b, v5.16b\n" - "sqdmulh v10.4s, v10.4s, v18.4s\n" + "sqrdmulh v10.4s, v10.4s, v18.4s\n" "and v17.16b, v9.16b, v5.16b\n" - "sqdmulh v8.4s, v8.4s, v18.4s\n" + "sqrdmulh v8.4s, v8.4s, v18.4s\n" "and v20.16b, v7.16b, v5.16b\n" - "sqdmulh v6.4s, v6.4s, v18.4s\n" + "sqrdmulh v6.4s, v6.4s, v18.4s\n" "sshr v23.4s, v23.4s, #0x1f\n" "and v19.16b, v21.16b, v29.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" @@ -2062,22 +2062,22 @@ void a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( "ld1 { v17.s }[0], [x5]\n" "ld1 { v5.s }[0], [x6]\n" "119:" // Oddments: Load requant params: Bit 2: End - "sqdmulh v11.4s, v11.4s, v17.4s\n" - "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqrdmulh v11.4s, v11.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" "add x21, x21, x2\n" "add x15, x15, x2\n" - "sqdmulh v9.4s, v9.4s, v17.4s\n" - "sqdmulh v7.4s, v7.4s, v17.4s\n" + "sqrdmulh v9.4s, v9.4s, v17.4s\n" + "sqrdmulh v7.4s, v7.4s, v17.4s\n" "add x17, x17, x2\n" "add x16, x16, x2\n" "and v23.16b, v11.16b, v5.16b\n" - "sqdmulh v21.4s, v21.4s, v18.4s\n" + "sqrdmulh v21.4s, v21.4s, v18.4s\n" "and v22.16b, v14.16b, v5.16b\n" - "sqdmulh v10.4s, v10.4s, v18.4s\n" + "sqrdmulh v10.4s, v10.4s, v18.4s\n" "and v17.16b, v9.16b, v5.16b\n" - "sqdmulh v8.4s, v8.4s, v18.4s\n" + "sqrdmulh v8.4s, v8.4s, v18.4s\n" "and v20.16b, v7.16b, v5.16b\n" - "sqdmulh v6.4s, v6.4s, v18.4s\n" + "sqrdmulh v6.4s, v6.4s, v18.4s\n" "sshr v23.4s, v23.4s, #0x1f\n" "and v19.16b, v21.16b, v29.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" |