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| author | ramelg01 <ramy.elgammal@arm.com> | 2022-05-04 15:12:21 +0100 |
|---|---|---|
| committer | Pablo Marquez Tello <pablo.tello@arm.com> | 2022-05-05 08:54:15 +0000 |
| commit | 638b7e4f6b1125b74f27f90dea2cd23eca52bfe8 (patch) | |
| tree | 68cf88a73c990ad580f200b6ddff76d50860c1ea /src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp | |
| parent | facd9dd4c75feb886240a2b55cefe55ccf773f63 (diff) | |
| download | ComputeLibrary-638b7e4f6b1125b74f27f90dea2cd23eca52bfe8.tar.gz | |
Fix for Neon™ Depthwise Android P VTS test failure
Resolves: COMPMID-5237
Signed-off-by: ramy.elgammal@arm.com
Change-Id: Ib1f5e262030e915a038cef587001708bbaf14c56
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7508
Reviewed-by: David Mansell
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp index 6934dffc98..bd6fa1d443 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst/generic.cpp @@ -504,24 +504,24 @@ void a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( "smlal2 v5.4s, v24.8h, v3.8h\n" "smlal v15.4s, v28.4h, v4.4h\n" "smlal v17.4s, v26.4h, v4.4h\n" - "sqdmulh v15.4s, v15.4s, v12.4s\n" + "sqrdmulh v15.4s, v15.4s, v12.4s\n" "smlal v10.4s, v24.4h, v4.4h\n" "smlal v6.4s, v27.4h, v4.4h\n" - "sqdmulh v17.4s, v17.4s, v12.4s\n" + "sqrdmulh v17.4s, v17.4s, v12.4s\n" "smlal2 v16.4s, v28.8h, v4.8h\n" "smlal2 v8.4s, v26.8h, v4.8h\n" - "sqdmulh v10.4s, v10.4s, v12.4s\n" + "sqrdmulh v10.4s, v10.4s, v12.4s\n" "smlal2 v7.4s, v24.8h, v4.8h\n" "smlal2 v5.4s, v27.8h, v4.8h\n" - "sqdmulh v6.4s, v6.4s, v12.4s\n" + "sqrdmulh v6.4s, v6.4s, v12.4s\n" "and v23.16b, v15.16b, v19.16b\n" - "sqdmulh v16.4s, v16.4s, v20.4s\n" + "sqrdmulh v16.4s, v16.4s, v20.4s\n" "and v22.16b, v17.16b, v19.16b\n" - "sqdmulh v8.4s, v8.4s, v20.4s\n" + "sqrdmulh v8.4s, v8.4s, v20.4s\n" "and v21.16b, v10.16b, v19.16b\n" - "sqdmulh v7.4s, v7.4s, v20.4s\n" + "sqrdmulh v7.4s, v7.4s, v20.4s\n" "and v26.16b, v6.16b, v19.16b\n" - "sqdmulh v5.4s, v5.4s, v20.4s\n" + "sqrdmulh v5.4s, v5.4s, v20.4s\n" "sshr v23.4s, v23.4s, #0x1f\n" "and v4.16b, v16.16b, v29.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" @@ -947,24 +947,24 @@ void a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( "smlal2 v5.4s, v24.8h, v3.8h\n" "smlal v15.4s, v28.4h, v4.4h\n" "smlal v17.4s, v26.4h, v4.4h\n" - "sqdmulh v15.4s, v15.4s, v12.4s\n" + "sqrdmulh v15.4s, v15.4s, v12.4s\n" "smlal v10.4s, v24.4h, v4.4h\n" "smlal v6.4s, v27.4h, v4.4h\n" - "sqdmulh v17.4s, v17.4s, v12.4s\n" + "sqrdmulh v17.4s, v17.4s, v12.4s\n" "smlal2 v16.4s, v28.8h, v4.8h\n" "smlal2 v8.4s, v26.8h, v4.8h\n" - "sqdmulh v10.4s, v10.4s, v12.4s\n" + "sqrdmulh v10.4s, v10.4s, v12.4s\n" "smlal2 v7.4s, v24.8h, v4.8h\n" "smlal2 v5.4s, v27.8h, v4.8h\n" - "sqdmulh v6.4s, v6.4s, v12.4s\n" + "sqrdmulh v6.4s, v6.4s, v12.4s\n" "and v23.16b, v15.16b, v19.16b\n" - "sqdmulh v16.4s, v16.4s, v20.4s\n" + "sqrdmulh v16.4s, v16.4s, v20.4s\n" "and v22.16b, v17.16b, v19.16b\n" - "sqdmulh v8.4s, v8.4s, v20.4s\n" + "sqrdmulh v8.4s, v8.4s, v20.4s\n" "and v21.16b, v10.16b, v19.16b\n" - "sqdmulh v7.4s, v7.4s, v20.4s\n" + "sqrdmulh v7.4s, v7.4s, v20.4s\n" "and v26.16b, v6.16b, v19.16b\n" - "sqdmulh v5.4s, v5.4s, v20.4s\n" + "sqrdmulh v5.4s, v5.4s, v20.4s\n" "sshr v23.4s, v23.4s, #0x1f\n" "and v4.16b, v16.16b, v29.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" @@ -2064,22 +2064,22 @@ void a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( "ld1 { v12.s }[0], [x10]\n" "ld1 { v19.s }[0], [x1]\n" "119:" // Oddments: Load requant params: Bit 2: End - "sqdmulh v15.4s, v15.4s, v12.4s\n" - "sqdmulh v17.4s, v17.4s, v12.4s\n" + "sqrdmulh v15.4s, v15.4s, v12.4s\n" + "sqrdmulh v17.4s, v17.4s, v12.4s\n" "add x16, x16, x22\n" "add x8, x8, x22\n" - "sqdmulh v10.4s, v10.4s, v12.4s\n" - "sqdmulh v6.4s, v6.4s, v12.4s\n" + "sqrdmulh v10.4s, v10.4s, v12.4s\n" + "sqrdmulh v6.4s, v6.4s, v12.4s\n" "add x4, x4, x22\n" "add x7, x7, x22\n" "and v23.16b, v15.16b, v19.16b\n" - "sqdmulh v16.4s, v16.4s, v20.4s\n" + "sqrdmulh v16.4s, v16.4s, v20.4s\n" "and v22.16b, v17.16b, v19.16b\n" - "sqdmulh v8.4s, v8.4s, v20.4s\n" + "sqrdmulh v8.4s, v8.4s, v20.4s\n" "and v21.16b, v10.16b, v19.16b\n" - "sqdmulh v7.4s, v7.4s, v20.4s\n" + "sqrdmulh v7.4s, v7.4s, v20.4s\n" "and v26.16b, v6.16b, v19.16b\n" - "sqdmulh v5.4s, v5.4s, v20.4s\n" + "sqrdmulh v5.4s, v5.4s, v20.4s\n" "sshr v23.4s, v23.4s, #0x1f\n" "and v4.16b, v16.16b, v29.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" |