Fix for Neon™ Depthwise Android P VTS test failure

Resolves: COMPMID-5237
Signed-off-by: ramy.elgammal@arm.com
Change-Id: Ib1f5e262030e915a038cef587001708bbaf14c56
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7508
Reviewed-by: David Mansell
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>

1 files changed, 24 insertions, 24 deletions

diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp
index 5499392d6d..0dc377c5c1 100644
--- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp
+++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp
@@ -269,7 +269,7 @@ void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
     "ldr q4, [x13, #0x10]\n"
     "smlal2 v10.4s, v24.8h, v7.8h\n"
     "smlal v22.4s, v24.4h, v1.4h\n"
-    "sqdmulh v15.4s, v15.4s, v19.4s\n"
+    "sqrdmulh v15.4s, v15.4s, v19.4s\n"
     "ldr q31, [x11, #0x10]\n"
     "smlal2 v21.4s, v24.8h, v1.8h\n"
     "ldr d24, [x22, x15]\n"
@@ -285,7 +285,7 @@ void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
     "add x17, x17, #0x48\n"
     "smlal v9.4s, v28.4h, v7.4h\n"
     "smlal2 v16.4s, v28.8h, v7.8h\n"
-    "sqdmulh v10.4s, v10.4s, v4.4s\n"
+    "sqrdmulh v10.4s, v10.4s, v4.4s\n"
     "subs x16, x16, #0x1\n"
     "smlal2 v21.4s, v25.8h, v6.8h\n"
     "ldr d25, [x20, x15]\n"
@@ -301,7 +301,7 @@ void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
     "ssubl v29.8h, v29.8b, v12.8b\n"
     "smlal2 v21.4s, v27.8h, v7.8h\n"
     "smlal2 v18.4s, v26.8h, v7.8h\n"
-    "sqdmulh v9.4s, v9.4s, v19.4s\n"
+    "sqrdmulh v9.4s, v9.4s, v19.4s\n"
     "add x15, x15, #0x8\n"
     "smlal v22.4s, v24.4h, v5.4h\n"
     "smlal v23.4s, v25.4h, v6.4h\n"
@@ -309,17 +309,17 @@ void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
     "add x11, x11, #0x20\n"
     "smlal2 v21.4s, v24.8h, v5.8h\n"
     "smlal2 v18.4s, v25.8h, v6.8h\n"
-    "sqdmulh v16.4s, v16.4s, v4.4s\n"
+    "sqrdmulh v16.4s, v16.4s, v4.4s\n"
     "smlal v22.4s, v25.4h, v8.4h\n"
     "smlal v23.4s, v29.4h, v8.4h\n"
-    "sqdmulh v22.4s, v22.4s, v19.4s\n"
+    "sqrdmulh v22.4s, v22.4s, v19.4s\n"
     "smlal2 v21.4s, v25.8h, v8.8h\n"
     "smlal2 v18.4s, v29.8h, v8.8h\n"
-    "sqdmulh v23.4s, v23.4s, v19.4s\n"
+    "sqrdmulh v23.4s, v23.4s, v19.4s\n"
     "and v29.16b, v22.16b, v0.16b\n"
-    "sqdmulh v21.4s, v21.4s, v4.4s\n"
+    "sqrdmulh v21.4s, v21.4s, v4.4s\n"
     "and v20.16b, v23.16b, v0.16b\n"
-    "sqdmulh v18.4s, v18.4s, v4.4s\n"
+    "sqrdmulh v18.4s, v18.4s, v4.4s\n"
     "and v19.16b, v10.16b, v31.16b\n"
     "sshr v28.4s, v28.4s, #0x1f\n"
     "and v4.16b, v16.16b, v31.16b\n"
@@ -521,7 +521,7 @@ void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
     "ldr q4, [x13, #0x10]\n"
     "smlal2 v10.4s, v24.8h, v7.8h\n"
     "smlal v22.4s, v24.4h, v1.4h\n"
-    "sqdmulh v15.4s, v15.4s, v19.4s\n"
+    "sqrdmulh v15.4s, v15.4s, v19.4s\n"
     "ldr q31, [x11, #0x10]\n"
     "smlal2 v21.4s, v24.8h, v1.8h\n"
     "ldr d24, [x22, x15]\n"
@@ -537,7 +537,7 @@ void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
     "tst x8, #0x7\n"
     "smlal v9.4s, v28.4h, v7.4h\n"
     "smlal2 v16.4s, v28.8h, v7.8h\n"
-    "sqdmulh v10.4s, v10.4s, v4.4s\n"
+    "sqrdmulh v10.4s, v10.4s, v4.4s\n"
     "add x13, x13, #0x20\n"
     "smlal2 v21.4s, v25.8h, v6.8h\n"
     "ldr d25, [x20, x15]\n"
@@ -553,24 +553,24 @@ void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
     "ssubl v29.8h, v29.8b, v12.8b\n"
     "smlal2 v21.4s, v27.8h, v7.8h\n"
     "smlal2 v18.4s, v26.8h, v7.8h\n"
-    "sqdmulh v9.4s, v9.4s, v19.4s\n"
+    "sqrdmulh v9.4s, v9.4s, v19.4s\n"
     "add x15, x15, #0x8\n"
     "smlal v22.4s, v24.4h, v5.4h\n"
     "smlal v23.4s, v25.4h, v6.4h\n"
     "and v28.16b, v9.16b, v0.16b\n"
     "smlal2 v21.4s, v24.8h, v5.8h\n"
     "smlal2 v18.4s, v25.8h, v6.8h\n"
-    "sqdmulh v16.4s, v16.4s, v4.4s\n"
+    "sqrdmulh v16.4s, v16.4s, v4.4s\n"
     "smlal v22.4s, v25.4h, v8.4h\n"
     "smlal v23.4s, v29.4h, v8.4h\n"
-    "sqdmulh v22.4s, v22.4s, v19.4s\n"
+    "sqrdmulh v22.4s, v22.4s, v19.4s\n"
     "smlal2 v21.4s, v25.8h, v8.8h\n"
     "smlal2 v18.4s, v29.8h, v8.8h\n"
-    "sqdmulh v23.4s, v23.4s, v19.4s\n"
+    "sqrdmulh v23.4s, v23.4s, v19.4s\n"
     "and v29.16b, v22.16b, v0.16b\n"
-    "sqdmulh v21.4s, v21.4s, v4.4s\n"
+    "sqrdmulh v21.4s, v21.4s, v4.4s\n"
     "and v20.16b, v23.16b, v0.16b\n"
-    "sqdmulh v18.4s, v18.4s, v4.4s\n"
+    "sqrdmulh v18.4s, v18.4s, v4.4s\n"
     "and v19.16b, v10.16b, v31.16b\n"
     "sshr v28.4s, v28.4s, #0x1f\n"
     "and v4.16b, v16.16b, v31.16b\n"
@@ -1274,22 +1274,22 @@ void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
     "ld1 { v19.s }[0], [x13]\n"
     "ld1 { v0.s }[0], [x11]\n"
     "83:"  // Oddments: Load requant params: Bit 2: End
-    "sqdmulh v15.4s, v15.4s, v19.4s\n"
-    "sqdmulh v9.4s, v9.4s, v19.4s\n"
+    "sqrdmulh v15.4s, v15.4s, v19.4s\n"
+    "sqrdmulh v9.4s, v9.4s, v19.4s\n"
     "add x10, x10, x14\n"
     "add x9, x9, x14\n"
-    "sqdmulh v22.4s, v22.4s, v19.4s\n"
-    "sqdmulh v23.4s, v23.4s, v19.4s\n"
+    "sqrdmulh v22.4s, v22.4s, v19.4s\n"
+    "sqrdmulh v23.4s, v23.4s, v19.4s\n"
     "add x28, x28, x14\n"
     "add x27, x27, x14\n"
     "and v30.16b, v15.16b, v0.16b\n"
-    "sqdmulh v10.4s, v10.4s, v4.4s\n"
+    "sqrdmulh v10.4s, v10.4s, v4.4s\n"
     "and v28.16b, v9.16b, v0.16b\n"
-    "sqdmulh v16.4s, v16.4s, v4.4s\n"
+    "sqrdmulh v16.4s, v16.4s, v4.4s\n"
     "and v29.16b, v22.16b, v0.16b\n"
-    "sqdmulh v21.4s, v21.4s, v4.4s\n"
+    "sqrdmulh v21.4s, v21.4s, v4.4s\n"
     "and v20.16b, v23.16b, v0.16b\n"
-    "sqdmulh v18.4s, v18.4s, v4.4s\n"
+    "sqrdmulh v18.4s, v18.4s, v4.4s\n"
     "sshr v30.4s, v30.4s, #0x1f\n"
     "and v19.16b, v10.16b, v31.16b\n"
     "sshr v28.4s, v28.4s, #0x1f\n"