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| author | Anthony Barbier <anthony.barbier@arm.com> | 2018-02-16 15:17:48 +0000 |
|---|---|---|
| committer | Anthony Barbier <anthony.barbier@arm.com> | 2018-11-02 16:47:18 +0000 |
| commit | 21f67d6763c82d78278f6bca6c6f9e42bb5ee1b9 (patch) | |
| tree | bc02a622f78ebec4b50b51708c94404ab0bef724 /src/core/CL | |
| parent | 7567f5f1919f69ea00c2cd5bdca65b67dfe6b388 (diff) | |
| download | ComputeLibrary-21f67d6763c82d78278f6bca6c6f9e42bb5ee1b9.tar.gz | |
COMPMID-934: Return an error in Validate when we don't support asymmetric padding
Currently an assert gets fired in debug mode, and we just ignore the asymmetric padding in release mode.
Change-Id: Ia6278b5722f7e93f356a975ab3243e6bb07e44a8
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/120840
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Tested-by: Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Diffstat (limited to 'src/core/CL')
| -rw-r--r-- | src/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.cpp | 2 | ||||
| -rw-r--r-- | src/core/CL/kernels/CLPoolingLayerKernel.cpp | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.cpp b/src/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.cpp index 4e2c4b5e74..650c5b89dc 100644 --- a/src/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.cpp +++ b/src/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.cpp @@ -42,12 +42,12 @@ Status CLDeconvolutionLayerUpsampleKernel::validate(const ITensorInfo *input, co const PadStrideInfo &info) { ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output); - ARM_COMPUTE_UNUSED(info); ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input, 1, DataType::F32); ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(input, output); ARM_COMPUTE_RETURN_ERROR_ON(output->dimension(0) == 0); ARM_COMPUTE_RETURN_ERROR_ON(output->dimension(1) == 0); + ARM_COMPUTE_RETURN_ERROR_ON(!info.padding_is_symmetric()); for(size_t i = 2; i < Coordinates::num_max_dimensions; ++i) { diff --git a/src/core/CL/kernels/CLPoolingLayerKernel.cpp b/src/core/CL/kernels/CLPoolingLayerKernel.cpp index bc5ff73b63..c515ed68e7 100644 --- a/src/core/CL/kernels/CLPoolingLayerKernel.cpp +++ b/src/core/CL/kernels/CLPoolingLayerKernel.cpp @@ -61,6 +61,7 @@ Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output, c ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input, 1, DataType::QASYMM8, DataType::QS8, DataType::QS16, DataType::F16, DataType::F32); ARM_COMPUTE_RETURN_ERROR_ON_MSG((is_data_type_quantized_asymmetric(input->data_type()) && pool_info.pool_type() == PoolingType::L2), "Unsupported combination of parameters!"); + ARM_COMPUTE_RETURN_ERROR_ON(!pool_info.pad_stride_info().padding_is_symmetric()); const bool is_global_pooling = pool_info.is_global_pooling(); const unsigned int pool_size_x = is_global_pooling ? input->tensor_shape().x() : pool_info.pool_size().width; |