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| author | Fadi Arafeh <fadi.arafeh@arm.com> | 2022-10-06 16:20:14 +0000 |
|---|---|---|
| committer | fadi.arafeh <fadi.arafeh@arm.com> | 2022-11-22 14:04:45 +0000 |
| commit | 73bb6b7ad80801e56633ad4ea12b0404b586a979 (patch) | |
| tree | 9f35a75499df4e1cc49cc6f3336c805384a53c13 /src/common | |
| parent | ca1a52d14551147456a9a1ea2e24f5c141a6d80e (diff) | |
| download | ComputeLibrary-73bb6b7ad80801e56633ad4ea12b0404b586a979.tar.gz | |
ONCPUML-1072: Tuned MWS values (for N1, V1) for binary operators used by oneDNN
Added approximate values for MWS for the following binary operators:
Add, Sub, Mul, Min, Max, Div
Change-Id: I5c4c75511129982a3f44c038ee272f09598469de
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/VisualCompute/ComputeLibrary/+/459609
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: bsgcomp <bsgcomp@arm.com>
Signed-off-by: fadara01 <fadi.arafeh@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8392
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/common')
| -rw-r--r-- | src/common/cpuinfo/CpuModel.cpp | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/common/cpuinfo/CpuModel.cpp b/src/common/cpuinfo/CpuModel.cpp index 6382ffd5b4..d6d91df133 100644 --- a/src/common/cpuinfo/CpuModel.cpp +++ b/src/common/cpuinfo/CpuModel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -54,6 +54,7 @@ bool model_supports_fp16(CpuModel model) case CpuModel::X1: case CpuModel::V1: case CpuModel::A64FX: + case CpuModel::N1: return true; default: return false; @@ -69,6 +70,7 @@ bool model_supports_dot(CpuModel model) case CpuModel::A510: case CpuModel::X1: case CpuModel::V1: + case CpuModel::N1: return true; default: return false; @@ -116,9 +118,11 @@ CpuModel midr_to_model(uint32_t midr) model = CpuModel::GENERIC_FP16; } break; + case 0xd0c: // N1 + model = CpuModel::N1; + break; case 0xd06: // A65 case 0xd0b: // A76 - case 0xd0c: // N1 case 0xd0d: // A77 case 0xd0e: // A76AE case 0xd41: // A78 |