APPBROWSER-391: Fix GLES COMPUTE alignment issues

APPBROWSER-402: Performance optimization for squeezenet/xray model

Change-Id: If31b186b99a6d6087164019fe94d3ac9279e3204
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/119526
Tested-by: Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>

7 files changed, 61 insertions, 20 deletions

diff --git a/arm_compute/core/GLES_COMPUTE/IGCTensor.h b/arm_compute/core/GLES_COMPUTE/IGCTensor.h
index ab4e57e0ce..7329864b85 100644
--- a/arm_compute/core/GLES_COMPUTE/IGCTensor.h
+++ b/arm_compute/core/GLES_COMPUTE/IGCTensor.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited.
+ * Copyright (c) 2017-2018 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -75,6 +75,18 @@ public:
      */
     virtual GLuint gc_buffer() const = 0;
 
+    /** Flag indicating whether the tensor has been left aligned by a kernel and therefore needs shifting.
+     *
+     * @return True if the tensor is left aligned.
+     */
+    bool needs_shifting() const;
+    /** Set the flag indicating whether or not a tensor needs shifting.
+     *
+     * @param[in] needs_shifting Indicates if the tensor is left aligned or not.
+     *
+     */
+    void set_needs_shifting(bool needs_shifting);
+
 protected:
     /** Method to be implemented by the child class to map the SSBO.
      *
@@ -92,6 +104,7 @@ protected:
 
 private:
     uint8_t *_mapping;
+    bool     _needs_shifting;
 };
 
 using IGCImage = IGCTensor;
diff --git a/arm_compute/core/GLES_COMPUTE/kernels/GCDepthConcatenateLayerKernel.h b/arm_compute/core/GLES_COMPUTE/kernels/GCDepthConcatenateLayerKernel.h
index ce220cc564..06a54dd0b3 100644
--- a/arm_compute/core/GLES_COMPUTE/kernels/GCDepthConcatenateLayerKernel.h
+++ b/arm_compute/core/GLES_COMPUTE/kernels/GCDepthConcatenateLayerKernel.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited.
+ * Copyright (c) 2017-2018 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -71,6 +71,7 @@ private:
     IGCTensor       *_output;
     int              _top_bottom;
     int              _left_right;
+    int              _depth_offset;
 };
 }
 #endif /* __ARM_COMPUTE_GCDEPTHCONCATENATEKERNEL_H__ */
diff --git a/arm_compute/core/GLES_COMPUTE/kernels/GCScaleKernel.h b/arm_compute/core/GLES_COMPUTE/kernels/GCScaleKernel.h
index 3f936f6cb9..bdbc50c735 100644
--- a/arm_compute/core/GLES_COMPUTE/kernels/GCScaleKernel.h
+++ b/arm_compute/core/GLES_COMPUTE/kernels/GCScaleKernel.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, 2017 ARM Limited.
+ * Copyright (c) 2016-2018 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -24,7 +24,7 @@
 #ifndef __ARM_COMPUTE_GCSCALEKERNEL_H__
 #define __ARM_COMPUTE_GCSCALEKERNEL_H__
 
-#include "arm_compute/core/GLES_COMPUTE/IGCSimple2DKernel.h"
+#include "arm_compute/core/GLES_COMPUTE/IGCSimple3DKernel.h"
 #include "arm_compute/core/Types.h"
 
 namespace arm_compute
@@ -32,7 +32,7 @@ namespace arm_compute
 class IGCTensor;
 
 /** Interface for the scale kernel */
-class GCScaleKernel : public IGCSimple2DKernel
+class GCScaleKernel : public IGCSimple3DKernel
 {
 public:
     /** Initialise the kernel's inputs, output and interpolation policy
@@ -47,6 +47,7 @@ public:
     void configure(const IGCTensor *input, IGCTensor *output, InterpolationPolicy policy, bool border_undefined, SamplingPolicy sampling_policy = SamplingPolicy::CENTER);
 
     // Inherited methods overridden:
+    void run(const Window &window) override;
     BorderSize border_size() const override;
 };
 } // namespace arm_compute
diff --git a/arm_compute/core/GLES_COMPUTE/kernels/GCTensorShiftKernel.h b/arm_compute/core/GLES_COMPUTE/kernels/GCTensorShiftKernel.h
index 5f108764b4..452caae146 100644
--- a/arm_compute/core/GLES_COMPUTE/kernels/GCTensorShiftKernel.h
+++ b/arm_compute/core/GLES_COMPUTE/kernels/GCTensorShiftKernel.h
@@ -78,6 +78,7 @@ public:
 private:
     IGCTensor    *_input;
     gles::NDRange _lws;
+    int           _left_padding;
 };
 }
 #endif /*__ARM_COMPUTE_GCTENSORSHIFTKERNEL_H__ */
diff --git a/arm_compute/runtime/GLES_COMPUTE/functions/GCDepthwiseConvolutionLayer.h b/arm_compute/runtime/GLES_COMPUTE/functions/GCDepthwiseConvolutionLayer.h
index 7b99ea5645..e523356fca 100644
--- a/arm_compute/runtime/GLES_COMPUTE/functions/GCDepthwiseConvolutionLayer.h
+++ b/arm_compute/runtime/GLES_COMPUTE/functions/GCDepthwiseConvolutionLayer.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited.
+ * Copyright (c) 2017-2018 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -25,8 +25,10 @@
 #define __ARM_COMPUTE_GCDEPTHWISECONVOLUTION_H__
 
 #include "arm_compute/core/GLES_COMPUTE/kernels/GCDepthwiseConvolutionLayer3x3Kernel.h"
+#include "arm_compute/core/GLES_COMPUTE/kernels/GCFillBorderKernel.h"
+#include "arm_compute/core/GLES_COMPUTE/kernels/GCTensorShiftKernel.h"
 #include "arm_compute/core/Types.h"
-#include "arm_compute/runtime/GLES_COMPUTE/IGCSimpleFunction.h"
+#include "arm_compute/runtime/IFunction.h"
 
 namespace arm_compute
 {
@@ -38,9 +40,11 @@ class IGCTensor;
  * -# @ref GCFillBorderKernel (if pad_x or pad_y > 0)
  *
  */
-class GCDepthwiseConvolutionLayer3x3 : public IGCSimpleFunction
+class GCDepthwiseConvolutionLayer3x3 : public IFunction
 {
 public:
+    /** Default constructor */
+    GCDepthwiseConvolutionLayer3x3();
     /** Initialize the function's source, destination, conv and border_size.
      *
      * @param[in, out] input     Source tensor. Data type supported: F16. (Written to only for border filling).
@@ -51,6 +55,14 @@ public:
      * @param[in]      conv_info Padding and stride information to use for the convolution.
      */
     void configure(IGCTensor *input, const IGCTensor *weights, const IGCTensor *biases, IGCTensor *output, const PadStrideInfo &conv_info);
+
+    // Inherited methods overridden:
+    void run() override final;
+
+private:
+    std::unique_ptr<IGCKernel> _kernel;
+    GCFillBorderKernel         _border_handler;
+    GCTensorShiftKernel        _shift_handler;
 };
 }
 #endif /*__ARM_COMPUTE_GCDEPTHWISECONVOLUTION_H__ */
diff --git a/arm_compute/runtime/GLES_COMPUTE/functions/GCDirectConvolutionLayer.h b/arm_compute/runtime/GLES_COMPUTE/functions/GCDirectConvolutionLayer.h
index c6b948be1f..976aee7b83 100644
--- a/arm_compute/runtime/GLES_COMPUTE/functions/GCDirectConvolutionLayer.h
+++ b/arm_compute/runtime/GLES_COMPUTE/functions/GCDirectConvolutionLayer.h
@@ -53,16 +53,17 @@ public:
     GCDirectConvolutionLayer();
     /** Set the input and output tensors.
      *
-     * @param[in]  input     Source tensor. 3 lower dimensions represent a single input [width, height, IFM],
-     *                       while every optional dimension from 4 and above represent a batch of inputs.
-     *                       Data types supported: F16/F32.
-     * @param[in]  weights   Weights tensor. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. Data type supported:Same as @p input.
-     * @param[in]  biases    Biases tensor. Shared biases supported. Biases are 1D tensor with dimensions [OFM]. Data type supported:Same as @p input.
-     * @param[out] output    Destination tensor. 3 lower dimensions represent a single output [width, height, OFM], while the rest represent batch of outputs.
-     *                       Data types supported: Same as @p input.
-     * @param[in]  conv_info Contains padding and stride information described in @ref PadStrideInfo.
+     * @param[in,out] input     Source tensor. 3 lower dimensions represent a single input [width, height, IFM],
+     *                          while every optional dimension from 4 and above represent a batch of inputs.
+     *                          Data types supported: F16/F32.
+     *                          input will be written to only if it is currently left aligned.
+     * @param[in]     weights   Weights tensor. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. Data type supported:Same as @p input.
+     * @param[in]     biases    Biases tensor. Shared biases supported. Biases are 1D tensor with dimensions [OFM]. Data type supported:Same as @p input.
+     * @param[out]    output    Destination tensor. 3 lower dimensions represent a single output [width, height, OFM], while the rest represent batch of outputs.
+     *                          Data types supported: Same as @p input.
+     * @param[in]     conv_info Contains padding and stride information described in @ref PadStrideInfo.
      */
-    void configure(const IGCTensor *input, const IGCTensor *weights, const IGCTensor *biases, IGCTensor *output, const PadStrideInfo &conv_info);
+    void configure(IGCTensor *input, const IGCTensor *weights, const IGCTensor *biases, IGCTensor *output, const PadStrideInfo &conv_info);
 
     // Inherited methods overridden:
     void run() override final;
diff --git a/arm_compute/runtime/GLES_COMPUTE/functions/GCPoolingLayer.h b/arm_compute/runtime/GLES_COMPUTE/functions/GCPoolingLayer.h
index 5733542a72..6f1dbb05bc 100644
--- a/arm_compute/runtime/GLES_COMPUTE/functions/GCPoolingLayer.h
+++ b/arm_compute/runtime/GLES_COMPUTE/functions/GCPoolingLayer.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited.
+ * Copyright (c) 2017-2018 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -24,7 +24,11 @@
 #ifndef __ARM_COMPUTE_GCPOOLINGLAYER_H__
 #define __ARM_COMPUTE_GCPOOLINGLAYER_H__
 
-#include "arm_compute/runtime/GLES_COMPUTE/IGCSimpleFunction.h"
+#include "arm_compute/core/GLES_COMPUTE/IGCKernel.h"
+#include "arm_compute/core/GLES_COMPUTE/kernels/GCFillBorderKernel.h"
+#include "arm_compute/core/GLES_COMPUTE/kernels/GCPoolingLayerKernel.h"
+#include "arm_compute/core/GLES_COMPUTE/kernels/GCTensorShiftKernel.h"
+#include "arm_compute/runtime/IFunction.h"
 
 #include "arm_compute/core/Error.h"
 #include "arm_compute/core/Types.h"
@@ -38,9 +42,10 @@ class IGCTensor;
  * -# @ref GCFillBorderKernel (executed if padding size is different from zero)
  * -# @ref GCPoolingLayerKernel
  */
-class GCPoolingLayer : public IGCSimpleFunction
+class GCPoolingLayer : public IFunction
 {
 public:
+    GCPoolingLayer();
     /** Set the input and output tensors.
      *
      * @param[in,out] input     Source tensor. (Written to only when padding != 0) Data types supported: F16/F32.
@@ -57,6 +62,13 @@ public:
      * @return a status
      */
     static Status validate(const ITensorInfo *input, const ITensorInfo *output, const PoolingLayerInfo &pool_info);
+
+    void run() override final;
+
+private:
+    std::unique_ptr<IGCKernel> _kernel;
+    GCFillBorderKernel         _border_handler;
+    GCTensorShiftKernel        _shift_handler;
 };
 } // namespace arm_compute
 #endif /* __ARM_COMPUTE_GCPOOLINGLAYER_H__ */