aboutsummaryrefslogtreecommitdiff
path: root/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h
diff options
context:
space:
mode:
authorMichele Di Giorgio <michele.digiorgio@arm.com>2021-01-19 15:29:02 +0000
committerSheri Zhang <sheri.zhang@arm.com>2021-01-19 18:21:47 +0000
commitbd2c8e1be0c83d243a9e2bc8eec60853f8dc701a (patch)
tree4e644b3bd1e0df1d05939d7e75a16be26d3d1c00 /arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h
parent0f7ef8ab2171093855a8f21bd39c8fd7066dd629 (diff)
downloadComputeLibrary-bd2c8e1be0c83d243a9e2bc8eec60853f8dc701a.tar.gz
Fix doxygen references to new kernels
Resolves COMPMID-4117 Change-Id: I9945a92402e34b9cfe0ba9ef2a961b168bf62721 Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com> Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4883 Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com> Comments-Addressed: Arm Jenkins <bsgcomp@arm.com> Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h')
-rw-r--r--arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h b/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h
index 59d83ed68d..aadc429864 100644
--- a/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -156,7 +156,7 @@ private:
* -# @ref NEGEMM (if the data type is BFLOAT16/FP16/FP32)
* -# @ref NEGEMMLowpMatrixMultiplyCore (if the data type is QASYMM8/QASYMM8_SIGNED)
* -# @ref NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPoint (if the data type is QASYMM8/QASYMM8_SIGNED)
- * -# @ref NEArithmeticAdditionKernel (if biases != nullptr and we have a 1x1 convolution with the NHWC data layout)
+ * -# @ref NEArithmeticAddition (if biases != nullptr and we have a 1x1 convolution with the NHWC data layout)
* -# @ref NECol2ImKernel (if NCHW data layout)
*
*/