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| author | Michalis Spyrou <michalis.spyrou@arm.com> | 2019-05-13 17:41:01 +0100 |
|---|---|---|
| committer | Michalis Spyrou <michalis.spyrou@arm.com> | 2019-05-20 13:59:51 +0000 |
| commit | b9626ab169a168a7c1ca57edd1996e1e80938bf1 (patch) | |
| tree | 57ce41fff5e2ece1e7d8f2a6f332c67e4534e752 /arm_compute/core | |
| parent | 0af4418f4d4b6bceaea64fa21eaf127b1b8fed35 (diff) | |
| download | ComputeLibrary-b9626ab169a168a7c1ca57edd1996e1e80938bf1.tar.gz | |
COMPMID-2243 ArgMinMaxLayer: support new datatypes
Change-Id: I846e833e0c94090cbbdcd6aee6061cea8295f4f9
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/1131
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'arm_compute/core')
| -rw-r--r-- | arm_compute/core/CL/kernels/CLReductionOperationKernel.h | 6 | ||||
| -rw-r--r-- | arm_compute/core/NEON/wrapper/intrinsics/inv.h | 10 |
2 files changed, 12 insertions, 4 deletions
diff --git a/arm_compute/core/CL/kernels/CLReductionOperationKernel.h b/arm_compute/core/CL/kernels/CLReductionOperationKernel.h index b5b90a15ce..aba11e1ad1 100644 --- a/arm_compute/core/CL/kernels/CLReductionOperationKernel.h +++ b/arm_compute/core/CL/kernels/CLReductionOperationKernel.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 ARM Limited. + * Copyright (c) 2017-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -50,7 +50,7 @@ public: /** Set the input and output tensors. * - * @param[in] input Source tensor. Data types supported: QASYMM8/F16/F32. + * @param[in] input Source tensor. Data types supported: QASYMM8/S32/F16/F32. * @param[out] output Destination tensor. Data types and data layouts supported: Same as @p input. * Output will have the same number of dimensions as input. * @param[in] axis Axis along which to reduce. Supported reduction axis : 0,1,2,3 @@ -61,7 +61,7 @@ public: /** Static function to check if given info will lead to a valid configuration of @ref CLReductionOperationKernel. * - * @param[in] input Source tensor info. Data types supported: QASYMM8/F16/F32. + * @param[in] input Source tensor info. Data types supported: QASYMM8/S32/F16/F32. * @param[in] output Destination tensor info. Data types and data layouts supported: Same as @p input. * Output will have the same number of dimensions as input. * @param[in] axis Axis along which to reduce. Supported reduction axis : 0,1,2,3 diff --git a/arm_compute/core/NEON/wrapper/intrinsics/inv.h b/arm_compute/core/NEON/wrapper/intrinsics/inv.h index a86a9d4671..acb2c91feb 100644 --- a/arm_compute/core/NEON/wrapper/intrinsics/inv.h +++ b/arm_compute/core/NEON/wrapper/intrinsics/inv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 ARM Limited. + * Copyright (c) 2018-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -37,12 +37,20 @@ namespace wrapper return prefix##_##postfix(a); \ } +#define VINV_IMPL_INT(vtype, prefix, postfix) \ + inline vtype vinv(const vtype &a) \ + { \ + ARM_COMPUTE_ERROR("Not supported"); \ + } + VINV_IMPL(float32x2_t, vinv, f32) +VINV_IMPL_INT(int32x2_t, vinv, s32) #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC VINV_IMPL(float16x4_t, vinv, f16) #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC VINV_IMPL(float32x4_t, vinvq, f32) +VINV_IMPL_INT(int32x4_t, vinvq, s32) #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC VINV_IMPL(float16x8_t, vinvq, f16) #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC |