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| author | SiCongLi <sicong.li@arm.com> | 2021-11-03 19:01:22 +0000 |
|---|---|---|
| committer | SiCong Li <sicong.li@arm.com> | 2021-11-04 14:03:19 +0000 |
| commit | d928735fee6baefdb74325c05d8152dd13044f32 (patch) | |
| tree | 6fb702e36da2863639149995e2df1cfe70905fc7 /arm_compute/core/experimental | |
| parent | 6049edadf0c89a026b3fcd1927ee7531d3c40278 (diff) | |
| download | ComputeLibrary-d928735fee6baefdb74325c05d8152dd13044f32.tar.gz | |
Add validate tests for CLConvolutionLayer and CLGEMMConvolutionLayer with post ops
* Add validate tests
* Restrict post ops support in ClGemmConv2d to only those that do not
need im2col or col2im. In practice this means we only support post ops
in conv1x1 with stride = 1, dilation = 1 and data layout = NHWC
Resolves COMPMID-4435
Change-Id: I1fdf0c5d565a4624857250075ac76db35c2f383b
Signed-off-by: SiCongLi <sicong.li@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6573
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'arm_compute/core/experimental')
| -rw-r--r-- | arm_compute/core/experimental/IPostOp.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arm_compute/core/experimental/IPostOp.h b/arm_compute/core/experimental/IPostOp.h index 178c83aa75..567a4023c0 100644 --- a/arm_compute/core/experimental/IPostOp.h +++ b/arm_compute/core/experimental/IPostOp.h @@ -71,6 +71,15 @@ using PostOpTypeSequence = std::vector<PostOpType>; * * post_op_arg1 = [1, 1, 34] is allowed: broadcast in dims 0 and 1 * * post_op_arg1 = [14, 15, 34] is NOT allowed: broadcast widens the dst tensor * + * @note: On Data layout + * All post ops are data layout agnostic. This means post ops do not have an inherent idea of "width", "height" and so on. + * Should we want to perform a post op with 2 tensors of different data layouts (where data layouts are significant to both), + * then we need to perform necessary permutation op beforehand to unify their data layout before they can be fused with a post op + * + * Note although post ops themselves should be able to support any data layout, the main op they fuse to may impose + * additional restrictions in the presence of post ops. For example, the implementation of a gemm op may only allow + * NHWC data layout if post ops are provided. Such restrictions are main op implementation specific. + * * @note: PostOps do not own any resources pointed to by TensorRelatedT if it's a pointer type * @note: If TensorRelatedT points to a resource, IPostOp assumes that resource is valid throughout its lifetime * and the lifetime of its copies. This is almost guaranteed as IPostOp is only meant to be used at configure time |