COMPMID-1975: Update depthwise convolution.

Change-Id: Iad58672be35710a7ec2e918653d6d529709387e8
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Reviewed-on: https://review.mlplatform.org/c/898
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>

4 files changed, 200 insertions, 34 deletions

diff --git a/arm_compute/core/NEON/kernels/convolution/common/activation.hpp b/arm_compute/core/NEON/kernels/convolution/common/activation.hpp
new file mode 100644
index 0000000000..091b1652c9
--- /dev/null
+++ b/arm_compute/core/NEON/kernels/convolution/common/activation.hpp
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#pragma once
+
+namespace neon_convolution_kernels
+{
+
+enum class ActivationFunction
+{
+  None,
+  ReLU,
+  ReLU6,
+};
+
+}
diff --git a/arm_compute/core/NEON/kernels/convolution/common/padding.hpp b/arm_compute/core/NEON/kernels/convolution/common/padding.hpp
new file mode 100644
index 0000000000..33f77d7ee9
--- /dev/null
+++ b/arm_compute/core/NEON/kernels/convolution/common/padding.hpp
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2019 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#pragma once
+
+#include <cstddef>
+
+// Utilities for copying tensor tiles and adding/removing padding.
+namespace padding
+{
+
+/* Copy a tile and apply padding to the output copy.
+ */
+template <typename T>
+void copy_and_pad_tile(
+  unsigned int tile_rows,
+  unsigned int tile_cols,
+  unsigned int n_channels,
+  const T *inptr,
+  unsigned int in_row_stride,
+  unsigned int in_col_stride,
+  T* outptr,
+  unsigned int out_row_stride,
+  unsigned int out_col_stride,
+  unsigned int pad_top,
+  unsigned int pad_left,
+  unsigned int pad_bottom,
+  unsigned int pad_right,
+  T pad_value=static_cast<T>(0)
+);
+
+/** Copy a tile and remove padding elements in the output.
+ */
+template <unsigned int TileRows, unsigned int TileCols>
+class CopyCropped
+{
+  public:
+    static void execute(
+      size_t size,  // Amount of data to copy
+      const void *inptr,
+      size_t in_row_stride,
+      size_t in_col_stride,
+      void *outptr,
+      size_t out_row_stride,
+      size_t out_col_stride,
+      unsigned int pad_top,
+      unsigned int pad_left,
+      unsigned int pad_bottom,
+      unsigned int pad_right
+    );
+};
+
+}
diff --git a/arm_compute/core/NEON/kernels/convolution/common/qasymm8.hpp b/arm_compute/core/NEON/kernels/convolution/common/qasymm8.hpp
new file mode 100644
index 0000000000..6029cb67e3
--- /dev/null
+++ b/arm_compute/core/NEON/kernels/convolution/common/qasymm8.hpp
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2019 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#pragma once
+#include <cstdint>
+
+namespace qasymm8
+{
+
+struct QAsymm8Params
+{
+  uint8_t quantize(float value) const;
+  float dequantize(uint8_t value) const;
+
+  uint8_t offset;
+  float scale;
+};
+
+struct QAsymm8RescaleParams
+{
+  static QAsymm8RescaleParams make_rescale_params(
+    const QAsymm8Params& weight_quant,
+    const QAsymm8Params& input_quant,
+    const QAsymm8Params& output_quant
+  );
+
+  QAsymm8RescaleParams(int32_t shift, int32_t multiplier, float rescale);
+
+  const int32_t shift, multiplier;
+  const float rescale;
+};
+
+}
diff --git a/arm_compute/core/NEON/kernels/convolution/common/tensor.hpp b/arm_compute/core/NEON/kernels/convolution/common/tensor.hpp
index 6567eeb23d..ad0a677a8f 100644
--- a/arm_compute/core/NEON/kernels/convolution/common/tensor.hpp
+++ b/arm_compute/core/NEON/kernels/convolution/common/tensor.hpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited.
+ * Copyright (c) 2017-2019 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -54,6 +54,18 @@ struct Tensor4DShape
   {
   }
 
+  inline int index(const int n, const int i, const int j, const int c) const
+  {
+    if (this->ordering == NHWC)
+    {
+      return ((n*this->n_rows + i)*this->n_cols + j)*this->n_channels + c;
+    }
+    else  // NCHW
+    {
+      return ((n*this->n_channels + c)*this->n_rows + i)*this->n_cols + j;
+    }
+  }
+
   inline int size() const
   {
     return n_batches * n_rows * n_cols * n_channels;
@@ -94,6 +106,18 @@ struct KernelShape
   {
   }
 
+  inline int index(int oc, int i, int j, int ic) const
+  {
+    if (this->ordering == HWIO)
+    {
+      return ((i*this->n_cols + j)*this->n_input_channels + ic)*this->n_output_channels + oc;
+    }
+    else  // OIHW
+    {
+      return ((oc*this->n_input_channels + ic)*this->n_rows + i)*this->n_cols + j;
+    }
+  }
+
   inline int size(void) const
   {
     return n_output_channels * n_rows * n_cols * n_input_channels;
@@ -127,7 +151,16 @@ class Tensor4D final
       return shape.size() * sizeof(T);
     }
 
-    inline T& element(int, int, int, int) const;
+    /* Extract an element of the tensor.
+     *
+     * If the shape is a Tensor4DShape then the index is given as batch, row,
+     * column and channel.  If the shape is a KernelShape then the index is
+     * given as output channel, row, column and input channel.
+     */
+    inline T& element(const int a, const int b, const int c, const int d) const
+    {
+      return _data[shape.index(a, b, c, d)];
+    }
 
     inline void Clear() {
       Fill(static_cast<T>(0));
@@ -143,35 +176,3 @@ class Tensor4D final
   private:
     T* const _data;
 };
-
-
-template <>
-inline float& Tensor4D<Tensor4DShape, float>::element(int n, int i, int j, int c) const
-{
-  int index;
-  if (shape.ordering == NHWC)
-  {
-    index = ((n*shape.n_rows + i)*shape.n_cols + j)*shape.n_channels + c;
-  }
-  else  // NCHW
-  {
-    index = ((n*shape.n_channels + c)*shape.n_rows + i)*shape.n_cols + j;
-  }
-  return _data[index];
-}
-
-
-template <>
-inline float& Tensor4D<KernelShape, float>::element(int oc, int i, int j, int ic) const
-{
-  int index;
-  if (shape.ordering == HWIO)
-  {
-    index = ((i*shape.n_cols + j)*shape.n_input_channels + ic)*shape.n_output_channels + oc;
-  }
-  else  // OIHW
-  {
-    index = ((oc*shape.n_input_channels + ic)*shape.n_rows + i)*shape.n_cols + j;
-  }
-  return _data[index];
-}