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| author | Michele Di Giorgio <michele.digiorgio@arm.com> | 2020-10-14 12:26:51 +0100 |
|---|---|---|
| committer | Michele Di Giorgio <michele.digiorgio@arm.com> | 2020-10-16 17:19:40 +0000 |
| commit | 671d4f01d96b62a24cf0688059118a1e7908650e (patch) | |
| tree | 33ee626be7de34f0c7fb91da9cb136004c361cb7 /arm_compute/core/CL | |
| parent | 3b9a564fd4573d7cf09e3203eb8a9a30fd5969c9 (diff) | |
| download | ComputeLibrary-671d4f01d96b62a24cf0688059118a1e7908650e.tar.gz | |
COMPMID-3724: Remove OpenCL padding: CLGEMMLowpQuantizeDownInt32ScaleByFloatKernel
COMPMID-3725: Remove OpenCL padding: CLGEMMLowpQuantizeDownInt32ScaleKernel
Change-Id: Idea5974a56861efae3bc255f1224c7f1e88f3650
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4182
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'arm_compute/core/CL')
| -rw-r--r-- | arm_compute/core/CL/kernels/CLGEMMLowpQuantizeDownInt32ScaleKernel.h | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/arm_compute/core/CL/kernels/CLGEMMLowpQuantizeDownInt32ScaleKernel.h b/arm_compute/core/CL/kernels/CLGEMMLowpQuantizeDownInt32ScaleKernel.h index 767d7927b4..1a284f0701 100644 --- a/arm_compute/core/CL/kernels/CLGEMMLowpQuantizeDownInt32ScaleKernel.h +++ b/arm_compute/core/CL/kernels/CLGEMMLowpQuantizeDownInt32ScaleKernel.h @@ -42,7 +42,7 @@ class ICLTensor; * -# Clamp the value between the specified min and max bounds * -# Clamp the resulting int32 values: * -# -to the [0..255] range and cast to QASYMM8. - * -# -to the [-128..127] range and cast to QASYMM8/SIGNED. + * -# -to the [-128..127] range and cast to QASYMM8_SIGNED. * */ class CLGEMMLowpQuantizeDownInt32ScaleKernel : public ICLKernel @@ -93,10 +93,9 @@ public: void run(const Window &window, cl::CommandQueue &queue) override; private: - const ICLTensor *_input; - const ICLTensor *_bias; - ICLTensor *_output; - const GEMMLowpOutputStageInfo *_output_stage; + const ICLTensor *_input; + const ICLTensor *_bias; + ICLTensor *_output; }; } // namespace arm_compute |