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author | Manuel Bottini <manuel.bottini@arm.com> | 2019-06-17 12:04:40 +0100 |
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committer | Georgios Pinitas <georgios.pinitas@arm.com> | 2019-07-11 16:14:01 +0000 |
commit | c1b76faf6be5c33dbf3269faea95e185ac37992f (patch) | |
tree | c52ecf022bf8b5e54844258744e6a10619b68d83 /arm_compute/core/CL/kernels | |
parent | 0ec65b8c6438b6d12f17487fdc4c870fe37c7caa (diff) | |
download | ComputeLibrary-c1b76faf6be5c33dbf3269faea95e185ac37992f.tar.gz |
COMPMID-2092: Refactoring interface for the deconvolution kernels (NEON/CL)
3RDPARTY_UPDATE
Change-Id: Id7ddf97e2c9ceb2cb84084fab2c6f5697890c193
Signed-off-by: giuros01 <giuseppe.rossini@arm.com>
Reviewed-on: https://review.mlplatform.org/c/1424
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Diffstat (limited to 'arm_compute/core/CL/kernels')
-rw-r--r-- | arm_compute/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.h | 21 |
1 files changed, 9 insertions, 12 deletions
diff --git a/arm_compute/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.h b/arm_compute/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.h index 5ccf4e64ed..21d026e0a1 100644 --- a/arm_compute/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.h +++ b/arm_compute/core/CL/kernels/CLDeconvolutionLayerUpsampleKernel.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 ARM Limited. + * Copyright (c) 2017-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -50,22 +50,20 @@ public: /** Initialise the kernel's input and output. * - * @param[in] input Source tensor. Data types supported: QASYMM8/F16/F32. - * @param[out] output Destination tensor. Data types supported: same as @p input. All but the lowest two dimensions must be the same size as in the input tensor, i.e. scaling is only performed within the XY-plane. - * @param[in] inner_border Top and right inner border sizes. These rows and columns will be filled with zero. - * @param[in] info Contains padding and stride information described in @ref PadStrideInfo. + * @param[in] input Source tensor. Data types supported: QASYMM8/F16/F32. + * @param[out] output Destination tensor. Data types supported: same as @p input. All but the lowest two dimensions must be the same size as in the input tensor, i.e. scaling is only performed within the XY-plane. + * @param[in] info Contains padding and stride information described in @ref PadStrideInfo. */ - void configure(const ICLTensor *input, ICLTensor *output, const BorderSize &inner_border, const PadStrideInfo &info); + void configure(const ICLTensor *input, ICLTensor *output, const PadStrideInfo &info); /** Static function to check if given info will lead to a valid configuration of @ref CLDeconvolutionLayerUpsample * - * @param[in] input Source tensor info. Data types supported: QASYMM8/F16/F32. - * @param[in] output Destination tensor info. Data types supported: same as @p input. All but the lowest two dimensions must be the same size as in the input tensor, i.e. scaling is only performed within the XY-plane. - * @param[in] inner_border Top and right inner border sizes. These rows and columns will be filled with zero. - * @param[in] info Contains padding and stride information described in @ref PadStrideInfo. + * @param[in] input Source tensor info. Data types supported: QASYMM8/F16/F32. + * @param[in] output Destination tensor info. Data types supported: same as @p input. All but the lowest two dimensions must be the same size as in the input tensor, i.e. scaling is only performed within the XY-plane. + * @param[in] info Contains padding and stride information described in @ref PadStrideInfo. * * @return a status */ - static Status validate(const ITensorInfo *input, const ITensorInfo *output, const BorderSize &inner_border, const PadStrideInfo &info); + static Status validate(const ITensorInfo *input, const ITensorInfo *output, const PadStrideInfo &info); // Inherited methods overridden: void run(const Window &window, cl::CommandQueue &queue) override; @@ -73,7 +71,6 @@ public: private: const ICLTensor *_input; ICLTensor *_output; - BorderSize _inner_border; PadStrideInfo _info; }; } // namespace arm_compute |