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authorMohammed Suhail Munshi <MohammedSuhail.Munshi@arm.com>2021-12-09 17:36:25 +0000
committerSheri Zhang <sheri.zhang@arm.com>2021-12-10 14:54:49 +0000
commitcff6f3b3d6750c47e9f8616bb8b2ec671cfe33d3 (patch)
treee7bbea9c31cc31b3bcf06d98db298568c3be8e51
parent8d07127f5c8f0e189ee0db4feb88c0c0b47608d5 (diff)
downloadComputeLibrary-cff6f3b3d6750c47e9f8616bb8b2ec671cfe33d3.tar.gz
Fix 300% Regression CPU - Change default mws value in Kernel files
Resolves: COMPMID-5001 Change-Id: I13fbe859d2557be0459ba76da0136d0efb15f311 Signed-off-by: Mohammed Suhail Munshi <MohammedSuhail.Munshi@arm.com> Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6809 Tested-by: Arm Jenkins <bsgcomp@arm.com> Comments-Addressed: Arm Jenkins <bsgcomp@arm.com> Reviewed-by: Sheri Zhang <sheri.zhang@arm.com>
-rw-r--r--arm_compute/core/CPP/CPPTypes.h1
-rw-r--r--src/core/NEON/kernels/NEPadLayerKernel.cpp6
-rw-r--r--src/cpu/kernels/CpuActivationKernel.cpp6
-rw-r--r--src/cpu/kernels/CpuAddKernel.cpp6
-rw-r--r--src/cpu/kernels/CpuIm2ColKernel.cpp6
-rw-r--r--src/cpu/kernels/CpuReshapeKernel.cpp6
-rw-r--r--src/cpu/kernels/assembly/CpuGemmAssemblyWrapperKernel.h6
-rw-r--r--src/cpu/kernels/internal/CpuDepthwiseConv2dAssemblyWrapperKernel.cpp6
8 files changed, 36 insertions, 7 deletions
diff --git a/arm_compute/core/CPP/CPPTypes.h b/arm_compute/core/CPP/CPPTypes.h
index 76378d27ef..82a6a6c324 100644
--- a/arm_compute/core/CPP/CPPTypes.h
+++ b/arm_compute/core/CPP/CPPTypes.h
@@ -39,6 +39,7 @@ namespace arm_compute
X(A55r1) \
X(A35) \
X(A73) \
+ X(A76) \
X(A510) \
X(X1) \
X(V1) \
diff --git a/src/core/NEON/kernels/NEPadLayerKernel.cpp b/src/core/NEON/kernels/NEPadLayerKernel.cpp
index 2e5e9f76be..4e689e74e4 100644
--- a/src/core/NEON/kernels/NEPadLayerKernel.cpp
+++ b/src/core/NEON/kernels/NEPadLayerKernel.cpp
@@ -267,10 +267,14 @@ size_t NEPadLayerKernel::get_mws(const CPUInfo &platform, size_t thread_count) c
{
return 10240;
}
- else
+ else if (platform.get_cpu_model() == CPUModel::A76)
{
return 9216;
}
+ else
+ {
+ return ICPPKernel::default_mws;
+ }
}
} // namespace arm_compute
diff --git a/src/cpu/kernels/CpuActivationKernel.cpp b/src/cpu/kernels/CpuActivationKernel.cpp
index 4a6468d022..aed73d1fec 100644
--- a/src/cpu/kernels/CpuActivationKernel.cpp
+++ b/src/cpu/kernels/CpuActivationKernel.cpp
@@ -238,10 +238,14 @@ size_t CpuActivationKernel::get_mws(const CPUInfo &platform, size_t thread_count
{
return 10240;
}
- else
+ else if (platform.get_cpu_model() == CPUModel::A76)
{
return 9216;
}
+ else
+ {
+ return ICPPKernel::default_mws;
+ }
}
void CpuActivationKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
diff --git a/src/cpu/kernels/CpuAddKernel.cpp b/src/cpu/kernels/CpuAddKernel.cpp
index 0c3540f0d4..f3ee032ec5 100644
--- a/src/cpu/kernels/CpuAddKernel.cpp
+++ b/src/cpu/kernels/CpuAddKernel.cpp
@@ -298,10 +298,14 @@ size_t CpuAddKernel::get_mws(const CPUInfo &platform, size_t thread_count) const
{
return 10240;
}
- else
+ else if (platform.get_cpu_model() == CPUModel::A76)
{
return 9216;
}
+ else
+ {
+ return ICPPKernel::default_mws;
+ }
}
} // namespace kernels
diff --git a/src/cpu/kernels/CpuIm2ColKernel.cpp b/src/cpu/kernels/CpuIm2ColKernel.cpp
index ecd1748a44..58890fe5a2 100644
--- a/src/cpu/kernels/CpuIm2ColKernel.cpp
+++ b/src/cpu/kernels/CpuIm2ColKernel.cpp
@@ -452,10 +452,14 @@ size_t CpuIm2ColKernel::get_mws(const CPUInfo &platform, size_t thread_count) co
{
return 10240;
}
- else
+ else if (platform.get_cpu_model() == CPUModel::A76)
{
return 9216;
}
+ else
+ {
+ return ICPPKernel::default_mws;
+ }
}
} // namespace kernels
} // namespace cpu
diff --git a/src/cpu/kernels/CpuReshapeKernel.cpp b/src/cpu/kernels/CpuReshapeKernel.cpp
index e19707dd0c..49cb91b330 100644
--- a/src/cpu/kernels/CpuReshapeKernel.cpp
+++ b/src/cpu/kernels/CpuReshapeKernel.cpp
@@ -143,10 +143,14 @@ size_t CpuReshapeKernel::get_mws(const CPUInfo &platform, size_t thread_count) c
{
return 10240;
}
- else
+ else if (platform.get_cpu_model() == CPUModel::A76)
{
return 9216;
}
+ else
+ {
+ return ICPPKernel::default_mws;
+ }
}
} // namespace kernels
diff --git a/src/cpu/kernels/assembly/CpuGemmAssemblyWrapperKernel.h b/src/cpu/kernels/assembly/CpuGemmAssemblyWrapperKernel.h
index 47548b2538..212fd79306 100644
--- a/src/cpu/kernels/assembly/CpuGemmAssemblyWrapperKernel.h
+++ b/src/cpu/kernels/assembly/CpuGemmAssemblyWrapperKernel.h
@@ -130,10 +130,14 @@ public:
{
return 3072;
}
- else
+ else if (platform.get_cpu_model() == CPUModel::A76)
{
return 4096;
}
+ else
+ {
+ return ICPPKernel::default_mws;
+ }
}
private:
diff --git a/src/cpu/kernels/internal/CpuDepthwiseConv2dAssemblyWrapperKernel.cpp b/src/cpu/kernels/internal/CpuDepthwiseConv2dAssemblyWrapperKernel.cpp
index 934e38b054..6c235df59f 100644
--- a/src/cpu/kernels/internal/CpuDepthwiseConv2dAssemblyWrapperKernel.cpp
+++ b/src/cpu/kernels/internal/CpuDepthwiseConv2dAssemblyWrapperKernel.cpp
@@ -363,10 +363,14 @@ size_t CpuDepthwiseConv2dAssemblyWrapperKernel::get_mws(const CPUInfo &platform,
{
return 10240;
}
- else
+ else if (platform.get_cpu_model() == CPUModel::A76)
{
return 9216;
}
+ else
+ {
+ return ICPPKernel::default_mws;
+ }
}
} // namespace kernels
} // namespace cpu