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authorSheri Zhang <sheri.zhang@arm.com>2021-02-10 15:32:38 +0000
committerMichele Di Giorgio <michele.digiorgio@arm.com>2021-02-22 11:12:23 +0000
commitac6499a474503dfcf587d95b85823aeb5861103f (patch)
treefc0bdc870d564ef45468a5033f954b10505ec956
parent669d17d9055089be1a20f6984630b95019fe2e78 (diff)
downloadComputeLibrary-ac6499a474503dfcf587d95b85823aeb5861103f.tar.gz
Comply with Trademark rules for use of Neon, Arm and Mali
Full trademarks available in README.md Resolves: COMPMID-4257 Signed-off-by: Sheri Zhang <sheri.zhang@arm.com> Change-Id: Ibfba2adf2eef3449433f467464ebd87d7198474d Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com> Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5116 Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com> Comments-Addressed: Arm Jenkins <bsgcomp@arm.com> Tested-by: Arm Jenkins <bsgcomp@arm.com>
-rw-r--r--README.md38
-rw-r--r--SConstruct4
-rw-r--r--arm_compute/core/ITensor.h4
-rw-r--r--arm_compute/graph/TypePrinter.h2
-rw-r--r--arm_compute/graph/Types.h2
-rw-r--r--arm_compute/graph/Utils.h4
-rw-r--r--arm_compute/graph/backends/NEON/NEDeviceBackend.h6
-rw-r--r--arm_compute/graph/backends/NEON/NEFunctionFactory.h4
-rw-r--r--arm_compute/graph/backends/NEON/NESubTensorHandle.h4
-rw-r--r--arm_compute/graph/backends/NEON/NETensorHandle.h4
-rw-r--r--arm_compute/runtime/CL/functions/CLGEMMLowpOutputStage.h4
-rw-r--r--arm_compute/runtime/CL/functions/CLHarrisCorners.h4
-rw-r--r--arm_compute/runtime/IFunction.h4
-rw-r--r--arm_compute/runtime/ITransformWeights.h4
-rw-r--r--arm_compute/runtime/NEON/INEOperator.h4
-rw-r--r--arm_compute/runtime/NEON/INESimpleFunction.h4
-rw-r--r--arm_compute/runtime/NEON/INESimpleFunctionNoBorder.h4
-rw-r--r--arm_compute/runtime/NEON/NEFunctions.h4
-rw-r--r--arm_compute/runtime/NEON/NEScheduler.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEArgMinMaxLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEBox3x3.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NECannyEdge.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEConvolution.h8
-rw-r--r--arm_compute/runtime/NEON/functions/NEConvolutionLayer.h6
-rw-r--r--arm_compute/runtime/NEON/functions/NEDeconvolutionLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEDepthwiseConvolutionLayer.h8
-rw-r--r--arm_compute/runtime/NEON/functions/NEDerivative.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEDilate.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEDirectConvolutionLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEEqualizeHistogram.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEErode.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEFFT1D.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEFFT2D.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEFFTConvolutionLayer.h8
-rw-r--r--arm_compute/runtime/NEON/functions/NEFastCorners.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEFullyConnectedLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEGEMM.h2
-rw-r--r--arm_compute/runtime/NEON/functions/NEGEMMConv2d.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h2
-rw-r--r--arm_compute/runtime/NEON/functions/NEGEMMLowpMatrixMultiplyCore.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEGEMMLowpOutputStage.h20
-rw-r--r--arm_compute/runtime/NEON/functions/NEGaussian3x3.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEGaussian5x5.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEGaussianPyramid.h6
-rw-r--r--arm_compute/runtime/NEON/functions/NEHOGDescriptor.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEHOGDetector.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEHOGGradient.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEHOGMultiDetection.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEHarrisCorners.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NELSTMLayerQuantized.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NELaplacianPyramid.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NELaplacianReconstruct.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEMaxUnpoolingLayer.h2
-rw-r--r--arm_compute/runtime/NEON/functions/NEMeanStdDev.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEMedian3x3.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEMinMaxLocation.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NENonLinearFilter.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NENonMaximaSuppression3x3.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NENormalizationLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEOpticalFlow.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEPadLayer.h2
-rw-r--r--arm_compute/runtime/NEON/functions/NEPermute.h2
-rw-r--r--arm_compute/runtime/NEON/functions/NEPoolingLayer.h2
-rw-r--r--arm_compute/runtime/NEON/functions/NEQLSTMLayer.h2
-rw-r--r--arm_compute/runtime/NEON/functions/NEQuantizationLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEROIAlignLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEROIPoolingLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEReductionOperation.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NERemap.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEScharr3x3.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NESobel3x3.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NESobel5x5.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NESobel7x7.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NESpaceToBatchLayer.h2
-rw-r--r--arm_compute/runtime/NEON/functions/NESpaceToDepthLayer.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NETranspose.h4
-rw-r--r--arm_compute/runtime/NEON/functions/NEWinogradConvolutionLayer.h4
-rw-r--r--docs/00_introduction.dox136
-rw-r--r--docs/01_library.dox24
-rw-r--r--docs/02_tests.dox2
-rw-r--r--docs/04_adding_operator.dox16
-rw-r--r--docs/06_functions_list.dox2
-rw-r--r--docs/07_errata.dox2
-rw-r--r--docs/ComputeLibrary.dir32
-rw-r--r--examples/neon_cnn.cpp4
-rw-r--r--examples/neon_copy_objects.cpp4
-rw-r--r--examples/neoncl_scale_median_gaussian.cpp12
-rw-r--r--[-rwxr-xr-x]scripts/include_functions_kernels.py2
-rw-r--r--src/core/CL/cl_kernels/helpers_asymm.h6
-rw-r--r--src/core/NEON/INEKernel.h4
-rw-r--r--src/core/NEON/INESimpleKernel.h4
-rw-r--r--src/core/NEON/NEKernels.h2
-rw-r--r--src/core/NEON/kernels/NEBatchNormalizationLayerKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEBox3x3Kernel.h8
-rw-r--r--src/core/NEON/kernels/NECannyEdgeKernel.h6
-rw-r--r--src/core/NEON/kernels/NEChannelShuffleLayerKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NECol2ImKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NECol2ImKernel.h4
-rw-r--r--src/core/NEON/kernels/NEConvertFullyConnectedWeightsKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEConvertQuantizedSignednessKernel.h2
-rw-r--r--src/core/NEON/kernels/NEConvolutionKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEDerivativeKernel.cpp6
-rw-r--r--src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp6
-rw-r--r--src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h4
-rw-r--r--src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h4
-rw-r--r--src/core/NEON/kernels/NEFastCornersKernel.h4
-rw-r--r--src/core/NEON/kernels/NEFillBorderKernel.cpp2
-rw-r--r--src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMLowpMatrixMultiplyKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMLowpOffsetContributionKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMLowpOffsetContributionOutputStageKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ScaleKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMLowpReductionKernel.h8
-rw-r--r--src/core/NEON/kernels/NEGEMMMatrixAdditionKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMMatrixMultiplyKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGEMMTranspose1xWKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEGEMMTranspose1xWKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGatherKernel.h4
-rw-r--r--src/core/NEON/kernels/NEGaussian3x3Kernel.h4
-rw-r--r--src/core/NEON/kernels/NEGaussian5x5Kernel.h6
-rw-r--r--src/core/NEON/kernels/NEGaussianPyramidKernel.h6
-rw-r--r--src/core/NEON/kernels/NEHOGDescriptorKernel.h6
-rw-r--r--src/core/NEON/kernels/NEHOGDetectorKernel.h4
-rw-r--r--src/core/NEON/kernels/NEHarrisCornersKernel.h4
-rw-r--r--src/core/NEON/kernels/NEIm2ColKernel.cpp2
-rw-r--r--src/core/NEON/kernels/NEInstanceNormalizationLayerKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NELKTrackerKernel.h4
-rw-r--r--src/core/NEON/kernels/NENonMaximaSuppression3x3Kernel.h8
-rw-r--r--src/core/NEON/kernels/NENormalizationLayerKernel.cpp6
-rw-r--r--src/core/NEON/kernels/NEPadLayerKernel.h4
-rw-r--r--src/core/NEON/kernels/NEQLSTMLayerNormalizationKernel.h4
-rw-r--r--src/core/NEON/kernels/NERangeKernel.cpp6
-rw-r--r--src/core/NEON/kernels/NEReductionOperationKernel.cpp8
-rw-r--r--src/core/NEON/kernels/NEReductionOperationKernel.h4
-rw-r--r--src/core/NEON/kernels/NERemapKernel.h4
-rw-r--r--src/core/NEON/kernels/NEReorgLayerKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEReverseKernel.cpp6
-rw-r--r--src/core/NEON/kernels/NEScaleKernel.h2
-rw-r--r--src/core/NEON/kernels/NEStackLayerKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEStackLayerKernel.h4
-rw-r--r--src/core/NEON/kernels/NEThresholdKernel.cpp6
-rw-r--r--src/core/NEON/kernels/NETileKernel.h4
-rw-r--r--src/core/NEON/kernels/NETransposeKernel.cpp10
-rw-r--r--src/core/NEON/kernels/NETransposeKernel.h4
-rw-r--r--src/core/NEON/kernels/NEWeightsReshapeKernel.cpp4
-rw-r--r--src/core/NEON/kernels/NEWeightsReshapeKernel.h4
-rw-r--r--src/core/NEON/kernels/NEWinogradConvolutionLayerKernel.h16
-rw-r--r--src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp2
-rw-r--r--src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp24
-rw-r--r--src/core/NEON/kernels/batchnormalization/impl/NEON/fp16.cpp4
-rw-r--r--src/core/NEON/kernels/batchnormalization/impl/NEON/fp32.cpp2
-rw-r--r--src/core/NEON/kernels/detail/NEActivationFunctionDetail.h28
-rw-r--r--src/core/NEON/wrapper/traits.h4
-rw-r--r--src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp2
-rw-r--r--src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp2
-rw-r--r--src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp2
-rw-r--r--src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp2
-rw-r--r--src/core/cpu/kernels/CpuReshapeKernel.cpp2
-rw-r--r--src/core/cpu/kernels/activation/NEON/fp16.cpp4
-rw-r--r--src/core/cpu/kernels/activation/NEON/fp32.cpp2
-rw-r--r--src/core/cpu/kernels/add/neon/list.h4
-rw-r--r--src/core/cpu/kernels/pooling/neon/quantized.h8
-rw-r--r--src/core/cpu/kernels/softmax/impl/NEON/list.h4
-rw-r--r--src/core/cpu/kernels/sub/neon/list.h4
-rw-r--r--src/graph/backends/NEON/NEDeviceBackend.cpp8
-rw-r--r--src/graph/backends/NEON/NEFunctionFactory.cpp8
-rw-r--r--src/graph/backends/NEON/NENodeValidator.cpp4
-rw-r--r--src/runtime/NEON/functions/NEConvolutionLayer.cpp4
-rw-r--r--src/runtime/NEON/functions/NEGEMMAssemblyDispatch.cpp2
-rw-r--r--src/runtime/NEON/functions/NEGEMMConv2d.cpp4
-rw-r--r--src/runtime/NEON/functions/NEGEMMConvolutionLayer.cpp4
-rw-r--r--src/runtime/cpu/operators/CpuPooling.h2
-rw-r--r--tests/benchmark/NEON/Scale.cpp4
-rw-r--r--tests/benchmark/fixtures/ScaleLayerFixture.h4
-rw-r--r--tests/datasets/ScaleValidationDataset.h6
-rw-r--r--tests/framework/SConscript2
-rw-r--r--tests/validation/GLES_COMPUTE/Scale.cpp4
-rw-r--r--tests/validation/NEON/AbsoluteDifference.cpp4
-rw-r--r--tests/validation/NEON/Accumulate.cpp4
-rw-r--r--tests/validation/NEON/ActivationLayer.cpp2
-rw-r--r--tests/validation/NEON/ArgMinMax.cpp4
-rw-r--r--tests/validation/NEON/ArithmeticAddition.cpp2
-rw-r--r--tests/validation/NEON/ArithmeticSubtraction.cpp4
-rw-r--r--tests/validation/NEON/BatchNormalizationLayer.cpp4
-rw-r--r--tests/validation/NEON/BatchToSpaceLayer.cpp4
-rw-r--r--tests/validation/NEON/BitwiseAnd.cpp4
-rw-r--r--tests/validation/NEON/BitwiseNot.cpp4
-rw-r--r--tests/validation/NEON/BitwiseOr.cpp4
-rw-r--r--tests/validation/NEON/BitwiseXor.cpp4
-rw-r--r--tests/validation/NEON/BoundingBoxTransform.cpp4
-rw-r--r--tests/validation/NEON/Cast.cpp4
-rw-r--r--tests/validation/NEON/ChannelCombine.cpp4
-rw-r--r--tests/validation/NEON/ChannelExtract.cpp4
-rw-r--r--tests/validation/NEON/ChannelShuffle.cpp4
-rw-r--r--tests/validation/NEON/ColorConvert.cpp4
-rw-r--r--tests/validation/NEON/ConvertFullyConnectedWeights.cpp4
-rw-r--r--tests/validation/NEON/Convolution.cpp6
-rw-r--r--tests/validation/NEON/ConvolutionLayer.cpp4
-rw-r--r--tests/validation/NEON/Copy.cpp4
-rw-r--r--tests/validation/NEON/CropResize.cpp4
-rw-r--r--tests/validation/NEON/DeconvolutionLayer.cpp4
-rw-r--r--tests/validation/NEON/DepthConvertLayer.cpp4
-rw-r--r--tests/validation/NEON/DepthToSpaceLayer.cpp4
-rw-r--r--tests/validation/NEON/DepthwiseConvolutionLayer.cpp4
-rw-r--r--tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp6
-rw-r--r--tests/validation/NEON/DequantizationLayer.cpp4
-rw-r--r--tests/validation/NEON/Derivative.cpp4
-rw-r--r--tests/validation/NEON/DetectionPostProcessLayer.cpp6
-rw-r--r--tests/validation/NEON/Dilate.cpp4
-rw-r--r--tests/validation/NEON/DilatedConvolutionLayer.cpp4
-rw-r--r--tests/validation/NEON/DirectConvolutionLayer.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseAbsoluteValue.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseDivision.cpp6
-rw-r--r--tests/validation/NEON/ElementwiseExpLayer.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseLog.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseMax.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseMin.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseNegation.cpp4
-rw-r--r--tests/validation/NEON/ElementwisePower.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseRound.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseRsqrtLayer.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseSin.cpp4
-rw-r--r--tests/validation/NEON/ElementwiseSquareDiff.cpp4
-rw-r--r--tests/validation/NEON/FFT.cpp4
-rw-r--r--tests/validation/NEON/Fill.cpp5
-rw-r--r--tests/validation/NEON/Flatten.cpp4
-rw-r--r--tests/validation/NEON/FuseBatchNormalization.cpp6
-rw-r--r--tests/validation/NEON/GEMMLowp.cpp4
-rw-r--r--tests/validation/NEON/Gather.cpp4
-rw-r--r--tests/validation/NEON/GenerateProposalsLayer.cpp4
-rw-r--r--tests/validation/NEON/HOGDetector.cpp4
-rw-r--r--tests/validation/NEON/Im2Col.cpp2
-rw-r--r--tests/validation/NEON/InstanceNormalizationLayer.cpp4
-rw-r--r--tests/validation/NEON/L2NormalizeLayer.cpp4
-rw-r--r--tests/validation/NEON/LSTMLayer.cpp4
-rw-r--r--tests/validation/NEON/LSTMLayerQuantized.cpp4
-rw-r--r--tests/validation/NEON/Logical.cpp6
-rw-r--r--tests/validation/NEON/MaxUnpoolingLayer.cpp4
-rw-r--r--tests/validation/NEON/MeanStdDevNormalizationLayer.cpp4
-rw-r--r--tests/validation/NEON/MinMaxLocation.cpp4
-rw-r--r--tests/validation/NEON/NormalizationLayer.cpp4
-rw-r--r--tests/validation/NEON/PReluLayer.cpp4
-rw-r--r--tests/validation/NEON/PadLayer.cpp4
-rw-r--r--tests/validation/NEON/PoolingLayer.cpp2
-rw-r--r--tests/validation/NEON/PriorBoxLayer.cpp4
-rw-r--r--tests/validation/NEON/QLSTMLayerNormalization.cpp8
-rw-r--r--tests/validation/NEON/QuantizationLayer.cpp2
-rw-r--r--tests/validation/NEON/RNNLayer.cpp2
-rw-r--r--tests/validation/NEON/ROIAlignLayer.cpp4
-rw-r--r--tests/validation/NEON/Range.cpp4
-rw-r--r--tests/validation/NEON/ReduceMean.cpp2
-rw-r--r--tests/validation/NEON/ReductionOperation.cpp4
-rw-r--r--tests/validation/NEON/ReorgLayer.cpp4
-rw-r--r--tests/validation/NEON/Reverse.cpp4
-rw-r--r--tests/validation/NEON/Scale.cpp4
-rw-r--r--tests/validation/NEON/Select.cpp4
-rw-r--r--tests/validation/NEON/Slice.cpp4
-rw-r--r--tests/validation/NEON/SpaceToBatchLayer.cpp4
-rw-r--r--tests/validation/NEON/SpaceToDepthLayer.cpp4
-rw-r--r--tests/validation/NEON/Split.cpp4
-rw-r--r--tests/validation/NEON/StackLayer.cpp4
-rw-r--r--tests/validation/NEON/StridedSlice.cpp4
-rw-r--r--tests/validation/NEON/Tile.cpp4
-rw-r--r--tests/validation/NEON/UNIT/DynamicTensor.cpp4
-rw-r--r--tests/validation/NEON/UNIT/RuntimeContext.cpp4
-rw-r--r--tests/validation/NEON/Unstack.cpp4
-rw-r--r--tests/validation/fixtures/DepthConvertLayerFixture.h6
-rw-r--r--tests/validation/reference/UtilsQuantizedAsymm.h4
-rw-r--r--utils/CommonGraphOptions.h2
-rw-r--r--utils/GraphUtils.h4
275 files changed, 730 insertions, 695 deletions
diff --git a/README.md b/README.md
index b07c9807b9..e44f3a5045 100644
--- a/README.md
+++ b/README.md
@@ -29,7 +29,30 @@ Documentation (API, changelogs, build guide, contribution guide, errata, etc.) a
Binaries available at https://github.com/ARM-software/ComputeLibrary/releases.
-License & Contributions: The software is provided under MIT license. Contributions to this project are accepted under the same license.
+### Supported Architectures/Technologies
+
+- Arm® CPUs:
+ - Arm® Cortex®-A processor family using Arm® Neon™ technology
+ - Arm® Cortex®-R processor family with Armv8-R AArch64 architecture using Arm® Neon™ technology
+ - Arm® Cortex®-X1 processor using Arm® Neon™ technology
+
+- Arm® Mali™ GPUs:
+ - Arm® Mali™-G processor family
+ - Arm® Mali™-T processor family
+
+- x86
+
+### Supported OS
+
+- Androidâ„¢
+- Bare Metal
+- Linux®
+- macOS®
+- Tizenâ„¢
+
+## License and Contributions
+
+The software is provided under MIT license. Contributions to this project are accepted under the same license.
### Public mailing list
For technical discussion, the ComputeLibrary project has a public mailing list: acl-dev@lists.linaro.org
@@ -44,3 +67,16 @@ To indicate that you agree to the the terms of the DCO, you "sign off" your cont
```Signed-off-by: John Doe <john.doe@example.org>```
You must use your real name, no pseudonyms or anonymous contributions are accepted.
+
+## Trademarks and Copyrights
+
+Android is a trademark of Google LLC.
+
+Arm, Cortex and Mali are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
+
+Linux® is the registered trademark of Linus Torvalds in the U.S. and other countries.
+
+Mac and macOS are trademarks of Apple Inc., registered in the U.S. and other
+countries.
+
+Tizen is a registered trademark of The Linux Foundation.
diff --git a/SConstruct b/SConstruct
index 5d2002a45d..274326f679 100644
--- a/SConstruct
+++ b/SConstruct
@@ -124,7 +124,7 @@ if env['build'] == "embed_only":
Return()
if env['neon'] and 'x86' in env['arch']:
- print("Cannot compile NEON for x86")
+ print("Cannot compile Neon for x86")
Exit(1)
if env['set_soname'] and not version_at_least(SCons.__version__, "2.4"):
@@ -290,7 +290,7 @@ if not GetOption("help"):
print("GCC 6.2.1 or newer is required to compile armv8.2-a code")
Exit(1)
elif env['arch'] == 'arm64-v8a' and not version_at_least(compiler_ver, '4.9'):
- print("GCC 4.9 or newer is required to compile NEON code for AArch64")
+ print("GCC 4.9 or newer is required to compile Neon code for AArch64")
Exit(1)
if version_at_least(compiler_ver, '6.1'):
diff --git a/arm_compute/core/ITensor.h b/arm_compute/core/ITensor.h
index 272b83d9c2..abcec60b79 100644
--- a/arm_compute/core/ITensor.h
+++ b/arm_compute/core/ITensor.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@ namespace arm_compute
{
class Coordinates;
-/** Interface for NEON tensor */
+/** Interface for Neon tensor */
class ITensor
{
public:
diff --git a/arm_compute/graph/TypePrinter.h b/arm_compute/graph/TypePrinter.h
index 1037c80157..3f529a9814 100644
--- a/arm_compute/graph/TypePrinter.h
+++ b/arm_compute/graph/TypePrinter.h
@@ -43,7 +43,7 @@ inline ::std::ostream &operator<<(::std::ostream &os, const Target &target)
os << "UNSPECIFIED";
break;
case Target::NEON:
- os << "NEON";
+ os << "Neon";
break;
case Target::CL:
os << "CL";
diff --git a/arm_compute/graph/Types.h b/arm_compute/graph/Types.h
index d1c71f815b..77e91b205a 100644
--- a/arm_compute/graph/Types.h
+++ b/arm_compute/graph/Types.h
@@ -94,7 +94,7 @@ struct GraphConfig
enum class Target
{
UNSPECIFIED, /**< Unspecified Target */
- NEON, /**< NEON capable target device */
+ NEON, /**< Neon capable target device */
CL, /**< OpenCL capable target device */
GC, /**< GLES compute capable target device */
};
diff --git a/arm_compute/graph/Utils.h b/arm_compute/graph/Utils.h
index b1be51ee30..e32ac29f35 100644
--- a/arm_compute/graph/Utils.h
+++ b/arm_compute/graph/Utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -76,7 +76,7 @@ bool is_target_supported(Target target);
/** Returns default target for execution
*
* @note If an OpenCL backend exists then OpenCL is returned,
- * else if the NEON backend exists returns NEON as target.
+ * else if the Neon backend exists returns Neon as target.
* If no backends are registered an error is raised.
*
* @return Default target
diff --git a/arm_compute/graph/backends/NEON/NEDeviceBackend.h b/arm_compute/graph/backends/NEON/NEDeviceBackend.h
index d0c8c27203..01d2be010a 100644
--- a/arm_compute/graph/backends/NEON/NEDeviceBackend.h
+++ b/arm_compute/graph/backends/NEON/NEDeviceBackend.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -34,7 +34,7 @@ namespace graph
{
namespace backends
{
-/** NEON device backend */
+/** Neon device backend */
class NEDeviceBackend final : public IDeviceBackend
{
public:
@@ -54,7 +54,7 @@ public:
std::shared_ptr<arm_compute::IWeightsManager> create_weights_manager() override;
private:
- Allocator _allocator; /**< NEON backend allocator */
+ Allocator _allocator; /**< Neon backend allocator */
};
} // namespace backends
} // namespace graph
diff --git a/arm_compute/graph/backends/NEON/NEFunctionFactory.h b/arm_compute/graph/backends/NEON/NEFunctionFactory.h
index 5d0e175fb0..4dd1f1f5ca 100644
--- a/arm_compute/graph/backends/NEON/NEFunctionFactory.h
+++ b/arm_compute/graph/backends/NEON/NEFunctionFactory.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -38,7 +38,7 @@ class GraphContext;
namespace backends
{
-/** Factory for generating NEON backend functions **/
+/** Factory for generating Neon backend functions **/
class NEFunctionFactory final
{
public:
diff --git a/arm_compute/graph/backends/NEON/NESubTensorHandle.h b/arm_compute/graph/backends/NEON/NESubTensorHandle.h
index 259be7822c..534f1c4e06 100644
--- a/arm_compute/graph/backends/NEON/NESubTensorHandle.h
+++ b/arm_compute/graph/backends/NEON/NESubTensorHandle.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -34,7 +34,7 @@ namespace graph
{
namespace backends
{
-/** NEON Sub-Tensor handle interface object **/
+/** Neon Sub-Tensor handle interface object **/
class NESubTensorHandle final : public ITensorHandle
{
public:
diff --git a/arm_compute/graph/backends/NEON/NETensorHandle.h b/arm_compute/graph/backends/NEON/NETensorHandle.h
index 86aba302a5..211990fe6c 100644
--- a/arm_compute/graph/backends/NEON/NETensorHandle.h
+++ b/arm_compute/graph/backends/NEON/NETensorHandle.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -34,7 +34,7 @@ namespace graph
{
namespace backends
{
-/** NEON Tensor handle interface object **/
+/** Neon Tensor handle interface object **/
class NETensorHandle final : public ITensorHandle
{
public:
diff --git a/arm_compute/runtime/CL/functions/CLGEMMLowpOutputStage.h b/arm_compute/runtime/CL/functions/CLGEMMLowpOutputStage.h
index a4edab9b8f..0f051ecffd 100644
--- a/arm_compute/runtime/CL/functions/CLGEMMLowpOutputStage.h
+++ b/arm_compute/runtime/CL/functions/CLGEMMLowpOutputStage.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -222,7 +222,7 @@ public:
*
* ((FixedPointMul(input[i][k] + bias[k], result_fixedpoint_multiplier)) >> result_shift) + result_offset_after_shift
*
- * This function calls the following NEON kernels:
+ * This function calls the following CL kernels:
*
* -# @ref CLGEMMLowpQuantizeDownInt32ScaleByFixedPointKernel
*
diff --git a/arm_compute/runtime/CL/functions/CLHarrisCorners.h b/arm_compute/runtime/CL/functions/CLHarrisCorners.h
index fc25c218ad..7f4a456eb3 100644
--- a/arm_compute/runtime/CL/functions/CLHarrisCorners.h
+++ b/arm_compute/runtime/CL/functions/CLHarrisCorners.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -44,7 +44,7 @@ class CLFillBorderKernel;
class ICLTensor;
using ICLImage = ICLTensor;
-/** Basic function to execute harris corners detection. This function calls the following CL and NEON kernels and functions:
+/** Basic function to execute harris corners detection. This function calls the following CL and Neon kernels and functions:
*
* @note Requires CPU support for the kernels: CPPCornerCandidatesKernel and CPPSortEuclideanDistanceKernel.
*
diff --git a/arm_compute/runtime/IFunction.h b/arm_compute/runtime/IFunction.h
index 265427e668..2aec0c007f 100644
--- a/arm_compute/runtime/IFunction.h
+++ b/arm_compute/runtime/IFunction.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -34,7 +34,7 @@ public:
virtual ~IFunction() = default;
/** Run the kernels contained in the function
*
- * For NEON kernels:
+ * For Neon kernels:
* - Multi-threading is used for the kernels which are parallelisable.
* - By default std::thread::hardware_concurrency() threads are used.
*
diff --git a/arm_compute/runtime/ITransformWeights.h b/arm_compute/runtime/ITransformWeights.h
index 9392be05e5..4fb2f89418 100644
--- a/arm_compute/runtime/ITransformWeights.h
+++ b/arm_compute/runtime/ITransformWeights.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -37,7 +37,7 @@ class ITensor;
* to generate a unique id. We use the following conversion using an unsigned 32bit value:
*
* Lower two bits store the target:
- * 00 -> NEON
+ * 00 -> Neon
* 01 -> CL
* 10 -> GLES
* 11 -> Unused
diff --git a/arm_compute/runtime/NEON/INEOperator.h b/arm_compute/runtime/NEON/INEOperator.h
index a5ffc74940..b21dc49b20 100644
--- a/arm_compute/runtime/NEON/INEOperator.h
+++ b/arm_compute/runtime/NEON/INEOperator.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -37,7 +37,7 @@ class ICPPKernel;
using INEKernel = ICPPKernel;
namespace experimental
{
-/** Basic interface for functions which have a single async NEON kernel */
+/** Basic interface for functions which have a single async Neon kernel */
class INEOperator : public IOperator
{
public:
diff --git a/arm_compute/runtime/NEON/INESimpleFunction.h b/arm_compute/runtime/NEON/INESimpleFunction.h
index 979a0f7f07..8c7cf6512c 100644
--- a/arm_compute/runtime/NEON/INESimpleFunction.h
+++ b/arm_compute/runtime/NEON/INESimpleFunction.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
class ICPPKernel;
class NEFillBorderKernel;
using INEKernel = ICPPKernel;
-/** Basic interface for functions which have a single NEON kernel */
+/** Basic interface for functions which have a single Neon kernel */
class INESimpleFunction : public IFunction
{
public:
diff --git a/arm_compute/runtime/NEON/INESimpleFunctionNoBorder.h b/arm_compute/runtime/NEON/INESimpleFunctionNoBorder.h
index 9df0d78526..52bd5f333b 100644
--- a/arm_compute/runtime/NEON/INESimpleFunctionNoBorder.h
+++ b/arm_compute/runtime/NEON/INESimpleFunctionNoBorder.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ICPPKernel;
using INEKernel = ICPPKernel;
-/** Basic interface for functions which have a single NEON kernel and no border */
+/** Basic interface for functions which have a single Neon kernel and no border */
class INESimpleFunctionNoBorder : public IFunction
{
public:
diff --git a/arm_compute/runtime/NEON/NEFunctions.h b/arm_compute/runtime/NEON/NEFunctions.h
index b7d05f9078..e876e3916f 100644
--- a/arm_compute/runtime/NEON/NEFunctions.h
+++ b/arm_compute/runtime/NEON/NEFunctions.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -24,7 +24,7 @@
#ifndef ARM_COMPUTE_NEFUNCTIONS_H
#define ARM_COMPUTE_NEFUNCTIONS_H
-/* Header regrouping all the NEON functions */
+/* Header regrouping all the Neon functions */
#include "arm_compute/runtime/NEON/functions/NEAbsoluteDifference.h"
#include "arm_compute/runtime/NEON/functions/NEAccumulate.h"
#include "arm_compute/runtime/NEON/functions/NEActivationLayer.h"
diff --git a/arm_compute/runtime/NEON/NEScheduler.h b/arm_compute/runtime/NEON/NEScheduler.h
index 13aa51f3d4..542142a30a 100644
--- a/arm_compute/runtime/NEON/NEScheduler.h
+++ b/arm_compute/runtime/NEON/NEScheduler.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@
namespace arm_compute
{
-/** NEON Scheduler */
+/** Neon Scheduler */
using NEScheduler = Scheduler;
}
#endif /*ARM_COMPUTE_NESCHEDULER_H */
diff --git a/arm_compute/runtime/NEON/functions/NEArgMinMaxLayer.h b/arm_compute/runtime/NEON/functions/NEArgMinMaxLayer.h
index 4b13d1f44e..8235185a8e 100644
--- a/arm_compute/runtime/NEON/functions/NEArgMinMaxLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEArgMinMaxLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -37,7 +37,7 @@ class ITensor;
/** Function to calculate the index of the minimum or maximum values in a
* tensor based on an axis.
*
- * This function calls the following NEON kernels:
+ * This function calls the following Neon kernels:
*
* -# @ref NEReductionOperationKernel
* -# @ref NEFillBorderKernel
diff --git a/arm_compute/runtime/NEON/functions/NEBox3x3.h b/arm_compute/runtime/NEON/functions/NEBox3x3.h
index d65c2be885..b45cf946e4 100644
--- a/arm_compute/runtime/NEON/functions/NEBox3x3.h
+++ b/arm_compute/runtime/NEON/functions/NEBox3x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute box filter 3x3. This function calls the following NEON kernels:
+/** Basic function to execute box filter 3x3. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEBox3x3Kernel
diff --git a/arm_compute/runtime/NEON/functions/NECannyEdge.h b/arm_compute/runtime/NEON/functions/NECannyEdge.h
index 7cdb8ee38e..2d8bac1db9 100644
--- a/arm_compute/runtime/NEON/functions/NECannyEdge.h
+++ b/arm_compute/runtime/NEON/functions/NECannyEdge.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -41,7 +41,7 @@ class NEFillBorderKernel;
class NEEdgeNonMaxSuppressionKernel;
class NEEdgeTraceKernel;
-/** Basic function to execute canny edge on NEON. This function calls the following NEON kernels and functions:
+/** Basic function to execute canny edge on Neon. This function calls the following Neon kernels and functions:
*
* -# @ref NEFillBorderKernel (if border_mode == REPLICATE or border_mode == CONSTANT)
* -# @ref NESobel3x3 (if gradient_size == 3) or
diff --git a/arm_compute/runtime/NEON/functions/NEConvolution.h b/arm_compute/runtime/NEON/functions/NEConvolution.h
index afd654a595..f2d7ae8090 100644
--- a/arm_compute/runtime/NEON/functions/NEConvolution.h
+++ b/arm_compute/runtime/NEON/functions/NEConvolution.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -45,7 +45,7 @@ class NESeparableConvolutionHorKernel;
template <unsigned int matrix_size>
class NESeparableConvolutionVertKernel;
-/** Basic function to execute convolution of size 3x3. This function calls the following NEON kernels:
+/** Basic function to execute convolution of size 3x3. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEConvolution3x3Kernel
@@ -80,7 +80,7 @@ public:
void configure(ITensor *input, ITensor *output, const int16_t *conv, uint32_t scale, BorderMode border_mode, uint8_t constant_border_value = 0);
};
-/** Basic function to execute convolution of size 5x5, 7x7, 9x9. This function calls the following NEON kernels:
+/** Basic function to execute convolution of size 5x5, 7x7, 9x9. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEConvolutionKernel or<br/>
@@ -136,7 +136,7 @@ using NEConvolution7x7 = NEConvolutionSquare<7>;
/** Basic function to run 9x9 convolution. */
using NEConvolution9x9 = NEConvolutionSquare<9>;
-/** Basic function to execute non-square convolution. This function calls the following NEON kernels:
+/** Basic function to execute non-square convolution. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEConvolutionRectangleKernel or<br/>
diff --git a/arm_compute/runtime/NEON/functions/NEConvolutionLayer.h b/arm_compute/runtime/NEON/functions/NEConvolutionLayer.h
index a061dc7b04..a387255b6c 100644
--- a/arm_compute/runtime/NEON/functions/NEConvolutionLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEConvolutionLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -37,7 +37,7 @@ namespace arm_compute
// Forward declarations
class ITensor;
-/** Basic function to simulate a convolution layer. This function calls one of the following NEON functions:
+/** Basic function to simulate a convolution layer. This function calls one of the following Neon functions:
* -# @ref NEGEMMConvolutionLayer (executed only in case GEMM is required for the operation)
* -# @ref NEWinogradConvolutionLayer (executed only in case Winograd is required for the operation)
* -# @ref NEDirectConvolutionLayer (executed only in case Direct Convolution is required for the operation)
@@ -158,4 +158,4 @@ private:
std::unique_ptr<IFunction> _function; /**< Function to run */
};
} // namespace arm_compute
-#endif /* ARM_COMPUTE_NECONVOLUTIONLAYER_H */ \ No newline at end of file
+#endif /* ARM_COMPUTE_NECONVOLUTIONLAYER_H */
diff --git a/arm_compute/runtime/NEON/functions/NEDeconvolutionLayer.h b/arm_compute/runtime/NEON/functions/NEDeconvolutionLayer.h
index 97b1a47f64..02a0f784ec 100644
--- a/arm_compute/runtime/NEON/functions/NEDeconvolutionLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEDeconvolutionLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -64,7 +64,7 @@ namespace arm_compute
* The weights used by Deconvolution are supposed to be the same as the ones used for Convolution. Therefore, it will be necessary to use the weights in the
* reverse order to perform an actual convolution. This is achieved by using @ref NEReverse.
*
- * This function calls the following NEON kernels/functions:
+ * This function calls the following Neon kernels/functions:
*
* -# @ref CPPUpsample
* -# @ref NEConvolutionLayer
diff --git a/arm_compute/runtime/NEON/functions/NEDepthwiseConvolutionLayer.h b/arm_compute/runtime/NEON/functions/NEDepthwiseConvolutionLayer.h
index dc70aec7ff..98fffe0b33 100644
--- a/arm_compute/runtime/NEON/functions/NEDepthwiseConvolutionLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEDepthwiseConvolutionLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -110,7 +110,7 @@ private:
const PadStrideInfo &conv_info, unsigned int depth_multiplier = 1,
ActivationLayerInfo act_info = ActivationLayerInfo(), const Size2D &dilation = Size2D(1U, 1U));
- /** Basic function to execute optimized depthwise convolution routines. This function calls the following NEON kernels:
+ /** Basic function to execute optimized depthwise convolution routines. This function calls the following Neon kernels:
*
* @note At the moment 3x3 and 5x5 convolution of stride 1, 2 are supported
*
@@ -192,7 +192,7 @@ private:
bool _is_prepared;
};
- /** Basic function to execute a generic depthwise convolution. This function calls the following NEON kernel:
+ /** Basic function to execute a generic depthwise convolution. This function calls the following Neon kernel:
*
* -# @ref NEDepthwiseConvolutionLayerNativeKernel
*
@@ -270,4 +270,4 @@ private:
NEDepthwiseConvolutionLayerGeneric _func_generic;
};
} // namespace arm_compute
-#endif /* ARM_COMPUTE_NEDEPTHWISECONVOLUTION_H */ \ No newline at end of file
+#endif /* ARM_COMPUTE_NEDEPTHWISECONVOLUTION_H */
diff --git a/arm_compute/runtime/NEON/functions/NEDerivative.h b/arm_compute/runtime/NEON/functions/NEDerivative.h
index b14e38a23a..c1e110b55b 100644
--- a/arm_compute/runtime/NEON/functions/NEDerivative.h
+++ b/arm_compute/runtime/NEON/functions/NEDerivative.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -35,7 +35,7 @@ class ITensor;
class NEDerivativeKernel;
class NEFillBorderKernel;
-/** Basic function to execute first order derivative operator. This function calls the following NEON kernels:
+/** Basic function to execute first order derivative operator. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEDerivativeKernel
diff --git a/arm_compute/runtime/NEON/functions/NEDilate.h b/arm_compute/runtime/NEON/functions/NEDilate.h
index 1f2bcb50ea..6c119d0d75 100644
--- a/arm_compute/runtime/NEON/functions/NEDilate.h
+++ b/arm_compute/runtime/NEON/functions/NEDilate.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute dilate. This function calls the following NEON kernels:
+/** Basic function to execute dilate. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEDilateKernel
diff --git a/arm_compute/runtime/NEON/functions/NEDirectConvolutionLayer.h b/arm_compute/runtime/NEON/functions/NEDirectConvolutionLayer.h
index 5b6ed55be2..ff0c3054d8 100644
--- a/arm_compute/runtime/NEON/functions/NEDirectConvolutionLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEDirectConvolutionLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -41,7 +41,7 @@ class NEFillBorderKernel;
/** Function to run the direct convolution.
*
- * This function calls the following NEON kernels:
+ * This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel for the input
* -# @ref NEDirectConvolutionLayerOutputStageKernel
diff --git a/arm_compute/runtime/NEON/functions/NEEqualizeHistogram.h b/arm_compute/runtime/NEON/functions/NEEqualizeHistogram.h
index e81b4ce33a..5d50651810 100644
--- a/arm_compute/runtime/NEON/functions/NEEqualizeHistogram.h
+++ b/arm_compute/runtime/NEON/functions/NEEqualizeHistogram.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -38,7 +38,7 @@ class NECumulativeDistributionKernel;
class NETableLookupKernel;
using IImage = ITensor;
-/** Basic function to execute histogram equalization. This function calls the following NEON kernels:
+/** Basic function to execute histogram equalization. This function calls the following Neon kernels:
*
* -# @ref NEHistogramKernel
* -# @ref NECumulativeDistributionKernel
diff --git a/arm_compute/runtime/NEON/functions/NEErode.h b/arm_compute/runtime/NEON/functions/NEErode.h
index b81da4e5b6..461bc878c9 100644
--- a/arm_compute/runtime/NEON/functions/NEErode.h
+++ b/arm_compute/runtime/NEON/functions/NEErode.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute erode. This function calls the following NEON kernels:
+/** Basic function to execute erode. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEErodeKernel
diff --git a/arm_compute/runtime/NEON/functions/NEFFT1D.h b/arm_compute/runtime/NEON/functions/NEFFT1D.h
index 4b6cc3fd18..04e8f81b69 100644
--- a/arm_compute/runtime/NEON/functions/NEFFT1D.h
+++ b/arm_compute/runtime/NEON/functions/NEFFT1D.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,7 @@ class NEFFTDigitReverseKernel;
class NEFFTRadixStageKernel;
class NEFFTScaleKernel;
-/** Basic function to execute one dimensional FFT. This function calls the following NEON kernels:
+/** Basic function to execute one dimensional FFT. This function calls the following Neon kernels:
*
* -# @ref NEFFTDigitReverseKernel Performs digit reverse
* -# @ref NEFFTRadixStageKernel A list of FFT kernels depending on the radix decomposition
diff --git a/arm_compute/runtime/NEON/functions/NEFFT2D.h b/arm_compute/runtime/NEON/functions/NEFFT2D.h
index 18e72c1a2f..218401b429 100644
--- a/arm_compute/runtime/NEON/functions/NEFFT2D.h
+++ b/arm_compute/runtime/NEON/functions/NEFFT2D.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -36,7 +36,7 @@ namespace arm_compute
// Forward declaration
class ITensor;
-/** Basic function to execute two dimensional FFT. This function calls the following NEON kernels:
+/** Basic function to execute two dimensional FFT. This function calls the following Neon kernels:
*
* -# @ref NEFFT1D 1D FFT is performed on the first given axis
* -# @ref NEFFT1D 1D FFT is performed on the second given axis
diff --git a/arm_compute/runtime/NEON/functions/NEFFTConvolutionLayer.h b/arm_compute/runtime/NEON/functions/NEFFTConvolutionLayer.h
index b181e05c1a..8967363e7f 100644
--- a/arm_compute/runtime/NEON/functions/NEFFTConvolutionLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEFFTConvolutionLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -43,7 +43,7 @@ namespace arm_compute
// Forward declarations
class ITensor;
-/** Basic function to execute FFT-based convolution on NEON. This function calls the following NEON functions/kernels:
+/** Basic function to execute FFT-based convolution on Neon. This function calls the following Neon functions/kernels:
*
* -# @ref NEPermute Permute input if NHWC(only NCHW is supported).
* -# @ref NEPadLayer Pad input.
@@ -84,7 +84,7 @@ public:
* Data types supported: Same as @p input.
* @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo.
* @param[in] act_info (Optional) Activation layer information in case of a fused activation.
- * @param[in] enable_fast_math (Optional) Enable fast math computation. Unused for NEON backend.
+ * @param[in] enable_fast_math (Optional) Enable fast math computation. Unused for Neon backend.
*/
void configure(ITensor *input, const ITensor *weights, const ITensor *biases, ITensor *output, const PadStrideInfo &conv_info,
const ActivationLayerInfo &act_info = ActivationLayerInfo(), bool enable_fast_math = false);
@@ -101,7 +101,7 @@ public:
* Data types supported: Same as @p input.
* @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo.
* @param[in] act_info (Optional) Activation layer information in case of a fused activation.
- * @param[in] enable_fast_math (Optional) Enable fast math computation. Unused for NEON backend.
+ * @param[in] enable_fast_math (Optional) Enable fast math computation. Unused for Neon backend.
*
* @return a status
*/
diff --git a/arm_compute/runtime/NEON/functions/NEFastCorners.h b/arm_compute/runtime/NEON/functions/NEFastCorners.h
index e86a87eb7e..c66aeedcca 100644
--- a/arm_compute/runtime/NEON/functions/NEFastCorners.h
+++ b/arm_compute/runtime/NEON/functions/NEFastCorners.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -43,7 +43,7 @@ class NEFillBorderKernel;
class NEFillArrayKernel;
using IImage = ITensor;
-/** Basic function to execute fast corners. This function call the following NEON kernels:
+/** Basic function to execute fast corners. This function call the following Neon kernels:
*
* -# @ref NEFastCornersKernel
* -# @ref NENonMaximaSuppression3x3Kernel (executed if nonmax_suppression == true)
diff --git a/arm_compute/runtime/NEON/functions/NEFullyConnectedLayer.h b/arm_compute/runtime/NEON/functions/NEFullyConnectedLayer.h
index 4a192688c7..ffea02670f 100644
--- a/arm_compute/runtime/NEON/functions/NEFullyConnectedLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEFullyConnectedLayer.h
@@ -36,7 +36,7 @@
namespace arm_compute
{
-/** Basic function to reshape the weights of Fully Connected layer with NEON. This function calls the following kernels:
+/** Basic function to reshape the weights of Fully Connected layer with Neon. This function calls the following kernels:
*
* @note The fully connected layer accepts "weights" tensors only with 2 dimensions.
*/
@@ -111,7 +111,7 @@ private:
};
} // namespace weights_transformations
-/** Basic function to compute a Fully Connected layer on NEON. This function calls the following NEON kernels:
+/** Basic function to compute a Fully Connected layer on Neon. This function calls the following Neon kernels:
* -# @ref NEIm2ColKernel (called when the input comes from a convolutional layer)
* -# @ref NEFullyConnectedLayerReshapeWeights (if @p are_weights_reshaped is set to false and transpose_weights is set to true ) (called once)
* -# @ref NEGEMMMatrixMultiplyKernel or @ref NEGEMMLowpMatrixMultiplyCore (if quantized asymmetric)
diff --git a/arm_compute/runtime/NEON/functions/NEGEMM.h b/arm_compute/runtime/NEON/functions/NEGEMM.h
index c67154c13a..6f7951eece 100644
--- a/arm_compute/runtime/NEON/functions/NEGEMM.h
+++ b/arm_compute/runtime/NEON/functions/NEGEMM.h
@@ -43,7 +43,7 @@ class NEGEMMMatrixMultiplyKernel;
class NEGEMMTranspose1xWKernel;
class NEGEMMAssemblyDispatch;
-/** Basic function to execute GEMM on NEON. This function calls the following NEON kernels:
+/** Basic function to execute GEMM on Neon. This function calls the following Neon kernels:
*
* If optimized assembly is available:
* -# @ref NEGEMMAssemblyDispatch
diff --git a/arm_compute/runtime/NEON/functions/NEGEMMConv2d.h b/arm_compute/runtime/NEON/functions/NEGEMMConv2d.h
index 2b3c162eab..2bd233f520 100644
--- a/arm_compute/runtime/NEON/functions/NEGEMMConv2d.h
+++ b/arm_compute/runtime/NEON/functions/NEGEMMConv2d.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -38,7 +38,7 @@ namespace arm_compute
class ITensor;
class NEGEMMAssemblyDispatch;
-/** Basic function to compute the convolution layer. This function calls the following NEON kernels/functions:
+/** Basic function to compute the convolution layer. This function calls the following Neon kernels/functions:
*
* Supports only NHWC data layout
*
diff --git a/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h b/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h
index 65c2ef7e0b..18ccc9f015 100644
--- a/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEGEMMConvolutionLayer.h
@@ -150,7 +150,7 @@ private:
};
} // namespace weights_transformations
-/** Basic function to compute the convolution layer. This function calls the following NEON kernels/functions:
+/** Basic function to compute the convolution layer. This function calls the following Neon kernels/functions:
*
* -# @ref NEIm2ColKernel
* -# @ref NEGEMM (if the data type is BFLOAT16/FP16/FP32)
diff --git a/arm_compute/runtime/NEON/functions/NEGEMMLowpMatrixMultiplyCore.h b/arm_compute/runtime/NEON/functions/NEGEMMLowpMatrixMultiplyCore.h
index 8eea9d7d24..821b498dad 100644
--- a/arm_compute/runtime/NEON/functions/NEGEMMLowpMatrixMultiplyCore.h
+++ b/arm_compute/runtime/NEON/functions/NEGEMMLowpMatrixMultiplyCore.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -47,7 +47,7 @@ class NEGEMMLowpMatrixBReductionKernel;
class NEGEMMTranspose1xWKernel;
class NEGEMMAssemblyDispatch;
-/** Basic function to execute GEMMLowpMatrixMultiplyCore on NEON. This function calls the following NEON kernels if the DOT product instruction is not available:
+/** Basic function to execute GEMMLowpMatrixMultiplyCore on Neon. This function calls the following Neon kernels if the DOT product instruction is not available:
*
* -# @ref NEGEMMInterleave4x4Kernel
* -# @ref NEGEMMTranspose1xWKernel
diff --git a/arm_compute/runtime/NEON/functions/NEGEMMLowpOutputStage.h b/arm_compute/runtime/NEON/functions/NEGEMMLowpOutputStage.h
index 6977d27cb6..79b427ea6f 100644
--- a/arm_compute/runtime/NEON/functions/NEGEMMLowpOutputStage.h
+++ b/arm_compute/runtime/NEON/functions/NEGEMMLowpOutputStage.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -27,7 +27,7 @@
#include "arm_compute/core/Types.h"
#include "arm_compute/runtime/NEON/INESimpleFunctionNoBorder.h"
-/** This file contains all available output stages for GEMMLowp on NEON.
+/** This file contains all available output stages for GEMMLowp on Neon.
*
* In gemmlowp, the "output stage" is the process that takes a final int32 accumulator value (the output of @ref NEGEMMLowpMatrixMultiplyCore),
* and processes it to obtain the final ASYMM8 value.
@@ -40,7 +40,7 @@ namespace arm_compute
class ITensor;
class ITensorInfo;
-/** Basic function to execute NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPoint on NEON.
+/** Basic function to execute NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPoint on Neon.
*
* NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPoint depends on 3 parameters:
*
@@ -61,7 +61,7 @@ class ITensorInfo;
*
* ((FixedPointMul(input[i][k] + bias[k], result_fixedpoint_multiplier)) >> result_shift) + result_offset_after_shift
*
- * This function calls the following NEON kernels:
+ * This function calls the following Neon kernels:
*
* -# @ref NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel
*
@@ -112,7 +112,7 @@ public:
*/
static Status validate(const ITensorInfo *input, const ITensorInfo *bias, const ITensorInfo *output, int min = std::numeric_limits<int32_t>::lowest(), int max = std::numeric_limits<int32_t>::max());
};
-/** Basic function to execute NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPoint on NEON.
+/** Basic function to execute NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPoint on Neon.
*
* NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPoint depends on 3 parameters:
*
@@ -133,7 +133,7 @@ public:
*
* ((FixedPointMul(input[i][k] + bias[k], result_fixedpoint_multiplier)) >> result_shift) + result_offset_after_shift
*
- * This function calls the following NEON kernels:
+ * This function calls the following Neon kernels:
*
* -# @ref NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel
*
@@ -184,7 +184,7 @@ public:
*/
static Status validate(const ITensorInfo *input, const ITensorInfo *bias, const ITensorInfo *output, int min = std::numeric_limits<int32_t>::lowest(), int max = std::numeric_limits<int32_t>::max());
};
-/** Basic function to execute NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPoint on NEON.
+/** Basic function to execute NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPoint on Neon.
*
* NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPoint depends on 2 parameters:
*
@@ -205,7 +205,7 @@ public:
*
* ((FixedPointMul(input[i][k] + bias[k], result_fixedpoint_multiplier)) >> result_shift) + result_offset_after_shift
*
- * This function calls the following NEON kernels:
+ * This function calls the following Neon kernels:
*
* -# @ref NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel
*
@@ -256,9 +256,9 @@ public:
static Status validate(const ITensorInfo *input, const ITensorInfo *bias, const ITensorInfo *output, int min = std::numeric_limits<int32_t>::lowest(), int max = std::numeric_limits<int32_t>::max());
};
-/** Basic function to execute GEMMLowpQuantizeDown kernels on NEON.
+/** Basic function to execute GEMMLowpQuantizeDown kernels on Neon.
*
- * This function calls the following NEON kernels:
+ * This function calls the following Neon kernels:
*
* -# @ref NEGEMMLowpQuantizeDownInt32ScaleKernel
* -# @ref NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel
diff --git a/arm_compute/runtime/NEON/functions/NEGaussian3x3.h b/arm_compute/runtime/NEON/functions/NEGaussian3x3.h
index 9341c76d85..8edf558db8 100644
--- a/arm_compute/runtime/NEON/functions/NEGaussian3x3.h
+++ b/arm_compute/runtime/NEON/functions/NEGaussian3x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute gaussian filter 3x3. This function calls the following NEON kernels:
+/** Basic function to execute gaussian filter 3x3. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEGaussian3x3Kernel
diff --git a/arm_compute/runtime/NEON/functions/NEGaussian5x5.h b/arm_compute/runtime/NEON/functions/NEGaussian5x5.h
index 51ebee3e8e..8ad9e9a7ed 100644
--- a/arm_compute/runtime/NEON/functions/NEGaussian5x5.h
+++ b/arm_compute/runtime/NEON/functions/NEGaussian5x5.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,7 @@ class NEGaussian5x5HorKernel;
class NEGaussian5x5VertKernel;
class NEFillBorderKernel;
-/** Basic function to execute gaussian filter 5x5. This function calls the following NEON kernels:
+/** Basic function to execute gaussian filter 5x5. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEGaussian5x5HorKernel
diff --git a/arm_compute/runtime/NEON/functions/NEGaussianPyramid.h b/arm_compute/runtime/NEON/functions/NEGaussianPyramid.h
index f5a1272b53..76a277782d 100644
--- a/arm_compute/runtime/NEON/functions/NEGaussianPyramid.h
+++ b/arm_compute/runtime/NEON/functions/NEGaussianPyramid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -79,7 +79,7 @@ protected:
Pyramid _tmp;
};
-/** Basic function to execute gaussian pyramid with HALF scale factor. This function calls the following NEON kernels:
+/** Basic function to execute gaussian pyramid with HALF scale factor. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEGaussianPyramidHorKernel
@@ -116,7 +116,7 @@ private:
std::vector<std::unique_ptr<NEGaussianPyramidVertKernel>> _vertical_reduction;
};
-/** Basic function to execute gaussian pyramid with ORB scale factor. This function calls the following NEON kernels and functions:
+/** Basic function to execute gaussian pyramid with ORB scale factor. This function calls the following Neon kernels and functions:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEGaussian5x5
diff --git a/arm_compute/runtime/NEON/functions/NEHOGDescriptor.h b/arm_compute/runtime/NEON/functions/NEHOGDescriptor.h
index a2d42fedf8..4f8d8a5f61 100644
--- a/arm_compute/runtime/NEON/functions/NEHOGDescriptor.h
+++ b/arm_compute/runtime/NEON/functions/NEHOGDescriptor.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -38,7 +38,7 @@ class IHOG;
class NEHOGOrientationBinningKernel;
class NEHOGBlockNormalizationKernel;
-/** Basic function to calculate HOG descriptor. This function calls the following NEON kernels:
+/** Basic function to calculate HOG descriptor. This function calls the following Neon kernels:
*
* -# @ref NEHOGGradient
* -# @ref NEHOGOrientationBinningKernel
diff --git a/arm_compute/runtime/NEON/functions/NEHOGDetector.h b/arm_compute/runtime/NEON/functions/NEHOGDetector.h
index 644851ee92..aea1d9f741 100644
--- a/arm_compute/runtime/NEON/functions/NEHOGDetector.h
+++ b/arm_compute/runtime/NEON/functions/NEHOGDetector.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@ namespace arm_compute
{
class ITensor;
class ITensorInfo;
-/** Basic function to execute HOG detector based on linear SVM. This function calls the following NEON kernel:
+/** Basic function to execute HOG detector based on linear SVM. This function calls the following Neon kernel:
*
* -# @ref NEHOGDetectorKernel
*
diff --git a/arm_compute/runtime/NEON/functions/NEHOGGradient.h b/arm_compute/runtime/NEON/functions/NEHOGGradient.h
index 426bc4b23c..16c1d24bca 100644
--- a/arm_compute/runtime/NEON/functions/NEHOGGradient.h
+++ b/arm_compute/runtime/NEON/functions/NEHOGGradient.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -39,7 +39,7 @@ namespace arm_compute
class ITensor;
class ICPPKernel;
-/** Basic function to calculate the gradient for HOG. This function calls the following NEON kernels:
+/** Basic function to calculate the gradient for HOG. This function calls the following Neon kernels:
*
* -# @ref NEDerivative
* -# NEMagnitudePhaseKernel
diff --git a/arm_compute/runtime/NEON/functions/NEHOGMultiDetection.h b/arm_compute/runtime/NEON/functions/NEHOGMultiDetection.h
index f370dd29ab..5b54d709e2 100644
--- a/arm_compute/runtime/NEON/functions/NEHOGMultiDetection.h
+++ b/arm_compute/runtime/NEON/functions/NEHOGMultiDetection.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -41,7 +41,7 @@ namespace arm_compute
class NEHOGOrientationBinningKernel;
class NEHOGBlockNormalizationKernel;
-/** Basic function to detect multiple objects (or the same object at different scales) on the same input image using HOG. This function calls the following NEON kernels:
+/** Basic function to detect multiple objects (or the same object at different scales) on the same input image using HOG. This function calls the following Neon kernels:
*
* -# @ref NEHOGGradient
* -# @ref NEHOGOrientationBinningKernel
diff --git a/arm_compute/runtime/NEON/functions/NEHarrisCorners.h b/arm_compute/runtime/NEON/functions/NEHarrisCorners.h
index 477b843aee..424d085737 100644
--- a/arm_compute/runtime/NEON/functions/NEHarrisCorners.h
+++ b/arm_compute/runtime/NEON/functions/NEHarrisCorners.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -44,7 +44,7 @@ class NEFillBorderKernel;
class INEHarrisScoreKernel;
using IImage = ITensor;
-/** Basic function to execute harris corners detection. This function calls the following NEON kernels and functions:
+/** Basic function to execute harris corners detection. This function calls the following Neon kernels and functions:
*
* -# @ref NESobel3x3 (if gradient_size == 3) or<br/>
* @ref NESobel5x5 (if gradient_size == 5) or<br/>
diff --git a/arm_compute/runtime/NEON/functions/NELSTMLayerQuantized.h b/arm_compute/runtime/NEON/functions/NELSTMLayerQuantized.h
index a354a4df7b..a59dcf88cc 100644
--- a/arm_compute/runtime/NEON/functions/NELSTMLayerQuantized.h
+++ b/arm_compute/runtime/NEON/functions/NELSTMLayerQuantized.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -47,7 +47,7 @@ class ITensor;
/** Basic function to run @ref NELSTMLayerQuantized
*
- * This function calls the following NEON functions/kernels:
+ * This function calls the following Neon functions/kernels:
*
* -# @ref NEGEMMLowpMatrixMultiplyCore Quantized matrix multiplication core. Accumulators are 32-bit integers
* -# @ref NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPoint Convert 32-bit integers into QSYMM16
diff --git a/arm_compute/runtime/NEON/functions/NELaplacianPyramid.h b/arm_compute/runtime/NEON/functions/NELaplacianPyramid.h
index 9ca30141a6..7c8f378d82 100644
--- a/arm_compute/runtime/NEON/functions/NELaplacianPyramid.h
+++ b/arm_compute/runtime/NEON/functions/NELaplacianPyramid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute laplacian pyramid. This function calls the following NEON kernels and functions:
+/** Basic function to execute laplacian pyramid. This function calls the following Neon kernels and functions:
*
* -# @ref NEGaussianPyramidHalf
* -# @ref NEGaussian5x5
diff --git a/arm_compute/runtime/NEON/functions/NELaplacianReconstruct.h b/arm_compute/runtime/NEON/functions/NELaplacianReconstruct.h
index 8e0a3efff0..9397dd1828 100644
--- a/arm_compute/runtime/NEON/functions/NELaplacianReconstruct.h
+++ b/arm_compute/runtime/NEON/functions/NELaplacianReconstruct.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -39,7 +39,7 @@ namespace arm_compute
class ITensor;
using IImage = ITensor;
-/** Basic function to execute laplacian reconstruction. This function calls the following NEON kernels and functions:
+/** Basic function to execute laplacian reconstruction. This function calls the following Neon kernels and functions:
*
* -# @ref NEArithmeticAddition
* -# @ref NEScale
diff --git a/arm_compute/runtime/NEON/functions/NEMaxUnpoolingLayer.h b/arm_compute/runtime/NEON/functions/NEMaxUnpoolingLayer.h
index 9626ca6f66..7b1f7e9ca1 100644
--- a/arm_compute/runtime/NEON/functions/NEMaxUnpoolingLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEMaxUnpoolingLayer.h
@@ -35,7 +35,7 @@ class ITensorInfo;
class NEFill;
class NEMaxUnpoolingLayerKernel;
-/** Function to perform MaxUnpooling. This function calls the following NEON kernels:
+/** Function to perform MaxUnpooling. This function calls the following Neon kernels:
*
* -# @ref NEFill
* -# @ref NEMaxUnpoolingLayerKernel
diff --git a/arm_compute/runtime/NEON/functions/NEMeanStdDev.h b/arm_compute/runtime/NEON/functions/NEMeanStdDev.h
index 875c3630c1..ce7bb8c5ee 100644
--- a/arm_compute/runtime/NEON/functions/NEMeanStdDev.h
+++ b/arm_compute/runtime/NEON/functions/NEMeanStdDev.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -36,7 +36,7 @@ namespace arm_compute
class NEMeanStdDevKernel;
class NEFillBorderKernel;
-/** Basic function to execute mean and std deviation. This function calls the following NEON kernels:
+/** Basic function to execute mean and std deviation. This function calls the following Neon kernels:
*
* @ref NEMeanStdDevKernel
*
diff --git a/arm_compute/runtime/NEON/functions/NEMedian3x3.h b/arm_compute/runtime/NEON/functions/NEMedian3x3.h
index 7e1ec905c6..90ee9ae5ef 100644
--- a/arm_compute/runtime/NEON/functions/NEMedian3x3.h
+++ b/arm_compute/runtime/NEON/functions/NEMedian3x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute median filter. This function calls the following NEON kernels:
+/** Basic function to execute median filter. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEMedian3x3Kernel
diff --git a/arm_compute/runtime/NEON/functions/NEMinMaxLocation.h b/arm_compute/runtime/NEON/functions/NEMinMaxLocation.h
index 312d1cb668..e1f765ebd4 100644
--- a/arm_compute/runtime/NEON/functions/NEMinMaxLocation.h
+++ b/arm_compute/runtime/NEON/functions/NEMinMaxLocation.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -38,7 +38,7 @@ class NEMinMaxKernel;
class NEMinMaxLocationKernel;
using IImage = ITensor;
-/** Basic function to execute min and max location. This function calls the following NEON kernels:
+/** Basic function to execute min and max location. This function calls the following Neon kernels:
*
* -# NEMinMaxKernel
* -# NEMinMaxLocationKernel
diff --git a/arm_compute/runtime/NEON/functions/NENonLinearFilter.h b/arm_compute/runtime/NEON/functions/NENonLinearFilter.h
index 8642350736..1cd523c4dd 100644
--- a/arm_compute/runtime/NEON/functions/NENonLinearFilter.h
+++ b/arm_compute/runtime/NEON/functions/NENonLinearFilter.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute non linear filter. This function calls the following NEON kernels:
+/** Basic function to execute non linear filter. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NENonLinearFilterKernel
diff --git a/arm_compute/runtime/NEON/functions/NENonMaximaSuppression3x3.h b/arm_compute/runtime/NEON/functions/NENonMaximaSuppression3x3.h
index 5b71d52e3e..2fff72d2ed 100644
--- a/arm_compute/runtime/NEON/functions/NENonMaximaSuppression3x3.h
+++ b/arm_compute/runtime/NEON/functions/NENonMaximaSuppression3x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -31,7 +31,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute non-maxima suppression over a 3x3 window. This function calls the following NEON kernels:
+/** Basic function to execute non-maxima suppression over a 3x3 window. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NENonMaximaSuppression3x3Kernel
diff --git a/arm_compute/runtime/NEON/functions/NENormalizationLayer.h b/arm_compute/runtime/NEON/functions/NENormalizationLayer.h
index 6519f9b4e6..fbc2f6f95b 100644
--- a/arm_compute/runtime/NEON/functions/NENormalizationLayer.h
+++ b/arm_compute/runtime/NEON/functions/NENormalizationLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -39,7 +39,7 @@ namespace arm_compute
class ITensor;
class NENormalizationLayerKernel;
-/** Basic function to compute a normalization layer. This function calls the following NEON kernels:
+/** Basic function to compute a normalization layer. This function calls the following Neon kernels:
*
* -# @ref NEPixelWiseMultiplication
* -# @ref NEFillBorderKernel
diff --git a/arm_compute/runtime/NEON/functions/NEOpticalFlow.h b/arm_compute/runtime/NEON/functions/NEOpticalFlow.h
index d1624ec68a..34f466b81c 100644
--- a/arm_compute/runtime/NEON/functions/NEOpticalFlow.h
+++ b/arm_compute/runtime/NEON/functions/NEOpticalFlow.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -45,7 +45,7 @@ class NELKTrackerKernel;
/** Array of LK Internel Keypoints */
using LKInternalKeypointArray = Array<NELKInternalKeypoint>;
-/** Basic function to execute optical flow. This function calls the following NEON kernels and functions:
+/** Basic function to execute optical flow. This function calls the following Neon kernels and functions:
*
* -# @ref NEScharr3x3
* -# @ref NELKTrackerKernel
diff --git a/arm_compute/runtime/NEON/functions/NEPadLayer.h b/arm_compute/runtime/NEON/functions/NEPadLayer.h
index ede9758202..242625604f 100644
--- a/arm_compute/runtime/NEON/functions/NEPadLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEPadLayer.h
@@ -38,7 +38,7 @@ namespace arm_compute
{
class NEPadLayerKernel;
-/** Basic function to pad a tensor. This function calls the following NEON functions/kernels:
+/** Basic function to pad a tensor. This function calls the following Neon functions/kernels:
*
* - For padding mode = PaddingMode::CONSTANT:
* -# @ref NEPadLayerKernel
diff --git a/arm_compute/runtime/NEON/functions/NEPermute.h b/arm_compute/runtime/NEON/functions/NEPermute.h
index e2e50f464f..cf7e25213b 100644
--- a/arm_compute/runtime/NEON/functions/NEPermute.h
+++ b/arm_compute/runtime/NEON/functions/NEPermute.h
@@ -52,7 +52,7 @@ public:
NEPermute &operator=(const NEPermute &) = delete;
/** Default move assignment operator */
NEPermute &operator=(NEPermute &&);
- /** Configure the permute NEON kernel
+ /** Configure the permute Neon kernel
*
* @note Arbitrary permutation vectors are supported with rank not greater than 4
*
diff --git a/arm_compute/runtime/NEON/functions/NEPoolingLayer.h b/arm_compute/runtime/NEON/functions/NEPoolingLayer.h
index 91b3a709f4..e374348f98 100644
--- a/arm_compute/runtime/NEON/functions/NEPoolingLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEPoolingLayer.h
@@ -36,7 +36,7 @@ namespace arm_compute
class ITensor;
class ITensorInfo;
-/** Basic function to simulate a pooling layer with the specified pooling operation. This function calls the following NEON kernels:
+/** Basic function to simulate a pooling layer with the specified pooling operation. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if padding size is different from zero)
* -# @ref cpu::kernels::CpuPoolingKernel
diff --git a/arm_compute/runtime/NEON/functions/NEQLSTMLayer.h b/arm_compute/runtime/NEON/functions/NEQLSTMLayer.h
index 743a32c47d..954aceba1a 100644
--- a/arm_compute/runtime/NEON/functions/NEQLSTMLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEQLSTMLayer.h
@@ -47,7 +47,7 @@ class NEGEMMLowpMatrixAReductionKernel;
/** Basic function to run @ref NEQLSTMLayer
*
- * This function calls the following NEON functions/kernels:
+ * This function calls the following Neon functions/kernels:
*
* -# @ref NEActivationLayer Activation functions (tanh and logistic)
* -# @ref NEArithmeticAddition Elementwise addition
diff --git a/arm_compute/runtime/NEON/functions/NEQuantizationLayer.h b/arm_compute/runtime/NEON/functions/NEQuantizationLayer.h
index 36302f4741..8b0532beea 100644
--- a/arm_compute/runtime/NEON/functions/NEQuantizationLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEQuantizationLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -35,7 +35,7 @@ namespace arm_compute
class ITensor;
class ITensorInfo;
-/** Basic function to simulate a quantization layer. This function calls the following NEON kernels:
+/** Basic function to simulate a quantization layer. This function calls the following Neon kernels:
*
*
* -# @ref NEQuantizationLayerKernel
diff --git a/arm_compute/runtime/NEON/functions/NEROIAlignLayer.h b/arm_compute/runtime/NEON/functions/NEROIAlignLayer.h
index ea3be18932..9d934588fb 100644
--- a/arm_compute/runtime/NEON/functions/NEROIAlignLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEROIAlignLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -34,7 +34,7 @@ class ITensorInfo;
/** Basic function to run @ref NEROIAlignLayerKernel.
*
- * This function calls the following NEON kernels:
+ * This function calls the following Neon kernels:
* -# @ref NEROIAlignLayerKernel
*
*/
diff --git a/arm_compute/runtime/NEON/functions/NEROIPoolingLayer.h b/arm_compute/runtime/NEON/functions/NEROIPoolingLayer.h
index 0b9b4f75fc..a912669f57 100644
--- a/arm_compute/runtime/NEON/functions/NEROIPoolingLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEROIPoolingLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -37,7 +37,7 @@ class ROIPoolingLayerInfo;
/** Basic function to run @ref NEROIPoolingLayerKernel.
*
- * This function calls the following NEON kernels:
+ * This function calls the following Neon kernels:
* -# @ref NEROIPoolingLayerKernel
*
*/
diff --git a/arm_compute/runtime/NEON/functions/NEReductionOperation.h b/arm_compute/runtime/NEON/functions/NEReductionOperation.h
index 8186e2e355..f30cc810f1 100644
--- a/arm_compute/runtime/NEON/functions/NEReductionOperation.h
+++ b/arm_compute/runtime/NEON/functions/NEReductionOperation.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -35,7 +35,7 @@ namespace arm_compute
class ITensor;
class NEReductionOperationKernel;
-/** Basic function to simulate a reduction operation. This function calls the following NEON kernels:
+/** Basic function to simulate a reduction operation. This function calls the following Neon kernels:
*
* -# @ref NEReshapeLayer
* -# @ref NEReductionOperationKernel
diff --git a/arm_compute/runtime/NEON/functions/NERemap.h b/arm_compute/runtime/NEON/functions/NERemap.h
index 86f366a697..84d0f2ee92 100644
--- a/arm_compute/runtime/NEON/functions/NERemap.h
+++ b/arm_compute/runtime/NEON/functions/NERemap.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -34,7 +34,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute remap. This function calls the following NEON kernels:
+/** Basic function to execute remap. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NERemapKernel
diff --git a/arm_compute/runtime/NEON/functions/NEScharr3x3.h b/arm_compute/runtime/NEON/functions/NEScharr3x3.h
index 8dd8a80287..e5ed1c7c5a 100644
--- a/arm_compute/runtime/NEON/functions/NEScharr3x3.h
+++ b/arm_compute/runtime/NEON/functions/NEScharr3x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute scharr 3x3 filter. This function calls the following NEON kernels:
+/** Basic function to execute scharr 3x3 filter. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NEScharr3x3Kernel
diff --git a/arm_compute/runtime/NEON/functions/NESobel3x3.h b/arm_compute/runtime/NEON/functions/NESobel3x3.h
index 89a2e07570..bc5f5e4545 100644
--- a/arm_compute/runtime/NEON/functions/NESobel3x3.h
+++ b/arm_compute/runtime/NEON/functions/NESobel3x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** Basic function to execute sobel 3x3 filter. This function calls the following NEON kernels:
+/** Basic function to execute sobel 3x3 filter. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NESobel3x3Kernel
diff --git a/arm_compute/runtime/NEON/functions/NESobel5x5.h b/arm_compute/runtime/NEON/functions/NESobel5x5.h
index 79e653b395..e64558c451 100644
--- a/arm_compute/runtime/NEON/functions/NESobel5x5.h
+++ b/arm_compute/runtime/NEON/functions/NESobel5x5.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,7 @@ class NESobel5x5HorKernel;
class NESobel5x5VertKernel;
class NEFillBorderKernel;
-/** Basic function to execute sobel 5x5 filter. This function calls the following NEON kernels:
+/** Basic function to execute sobel 5x5 filter. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NESobel5x5HorKernel
diff --git a/arm_compute/runtime/NEON/functions/NESobel7x7.h b/arm_compute/runtime/NEON/functions/NESobel7x7.h
index 7395bb0198..6419d67b56 100644
--- a/arm_compute/runtime/NEON/functions/NESobel7x7.h
+++ b/arm_compute/runtime/NEON/functions/NESobel7x7.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,7 @@ class NESobel7x7HorKernel;
class NESobel7x7VertKernel;
class NEFillBorderKernel;
-/** Basic function to execute sobel 7x7 filter. This function calls the following NEON kernels:
+/** Basic function to execute sobel 7x7 filter. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if border_mode == CONSTANT or border_mode == REPLICATE)
* -# @ref NESobel7x7HorKernel
diff --git a/arm_compute/runtime/NEON/functions/NESpaceToBatchLayer.h b/arm_compute/runtime/NEON/functions/NESpaceToBatchLayer.h
index 6a38dfba1e..aeeaefcc38 100644
--- a/arm_compute/runtime/NEON/functions/NESpaceToBatchLayer.h
+++ b/arm_compute/runtime/NEON/functions/NESpaceToBatchLayer.h
@@ -36,7 +36,7 @@ class ITensorInfo;
class NESpaceToBatchLayerKernel;
class NEFill;
-/** Basic function to spatial divide a tensor. This function calls the following NEON kernels/functions:
+/** Basic function to spatial divide a tensor. This function calls the following Neon kernels/functions:
*
* -# @ref NEFill
* -# @ref NESpaceToBatchLayerKernel
diff --git a/arm_compute/runtime/NEON/functions/NESpaceToDepthLayer.h b/arm_compute/runtime/NEON/functions/NESpaceToDepthLayer.h
index 1e7aae215d..d76fc48204 100644
--- a/arm_compute/runtime/NEON/functions/NESpaceToDepthLayer.h
+++ b/arm_compute/runtime/NEON/functions/NESpaceToDepthLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -35,7 +35,7 @@ class ITensor;
class ITensorInfo;
class NESpaceToDepthLayerKernel;
-/** This function calls the following NEON kernels/functions:
+/** This function calls the following Neon kernels/functions:
*
* -# @ref NESpaceToDepthLayerKernel
*/
diff --git a/arm_compute/runtime/NEON/functions/NETranspose.h b/arm_compute/runtime/NEON/functions/NETranspose.h
index 2651bdd727..fac1d406fb 100644
--- a/arm_compute/runtime/NEON/functions/NETranspose.h
+++ b/arm_compute/runtime/NEON/functions/NETranspose.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@ namespace arm_compute
class ITensor;
class ITensorInfo;
-/** Basic function to transpose a matrix on NEON. This function calls the following NEON kernel:
+/** Basic function to transpose a matrix on Neon. This function calls the following Neon kernel:
*
* -# @ref NETransposeKernel
*
diff --git a/arm_compute/runtime/NEON/functions/NEWinogradConvolutionLayer.h b/arm_compute/runtime/NEON/functions/NEWinogradConvolutionLayer.h
index 6b61e7031b..e41cdbd0ac 100644
--- a/arm_compute/runtime/NEON/functions/NEWinogradConvolutionLayer.h
+++ b/arm_compute/runtime/NEON/functions/NEWinogradConvolutionLayer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -42,7 +42,7 @@ namespace arm_compute
class ITensor;
class ICPPKernel;
-/** Basic function to simulate a convolution layer. This function calls the following NEON kernels:
+/** Basic function to simulate a convolution layer. This function calls the following Neon kernels:
* -# @ref NEWinogradLayerTransformWeightsKernel (executed only once in the first call to the run() method )
* -# @ref NEWinogradLayerTransformInputKernel
* -# @ref NEWinogradLayerTransformOutputKernel
diff --git a/docs/00_introduction.dox b/docs/00_introduction.dox
index 45824b1f42..389757e9d9 100644
--- a/docs/00_introduction.dox
+++ b/docs/00_introduction.dox
@@ -27,12 +27,12 @@ namespace arm_compute
@tableofcontents
-The Computer Vision and Machine Learning library is a set of functions optimised for both ARM CPUs and GPUs using SIMD technologies.
+The Computer Vision and Machine Learning library is a set of functions optimised for both Arm CPUs and GPUs using SIMD technologies.
Several builds of the library are available using various configurations:
- - OS: Linux, Android, macOS or bare metal.
- - Architecture: armv7a (32bit) or arm64-v8a (64bit)
- - Technology: NEON / OpenCL / GLES_COMPUTE / NEON and OpenCL and GLES_COMPUTE
+ - OS: Android or Linux.
+ - Architecture: armv7a (32bit) or arm64-v8a (64bit).
+ - Technology: Neon / OpenCL / Neon and OpenCL.
- Debug / Asserts / Release: Use a build with asserts enabled to debug your application and enable extra validation. Once you are sure your application works as expected you can switch to a release build of the library for maximum performance.
@section S0_1_contact Contact / Support
@@ -161,11 +161,11 @@ v20.11 Public major release
- @ref CLLogicalNot
- @ref CLLogicalAnd
- @ref CLLogicalOr
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- @ref NELogicalNot
- @ref NELogicalAnd
- @ref NELogicalOr
- - Removed padding from NEON kernels:
+ - Removed padding from Neon kernels:
- @ref NEComplexPixelWiseMultiplicationKernel
- @ref NENonMaximaSuppression3x3Kernel
- @ref NERemapKernel
@@ -315,7 +315,7 @@ v20.11 Public major release
- CLWarpAffineKernel
- CLWarpPerspective
- CLWarpPerspectiveKernel
- - Deprecated NEON kernels / functions (If a kernel is used only by the function that is being deprecated, the kernel is deprecated together):
+ - Deprecated Neon kernels / functions (If a kernel is used only by the function that is being deprecated, the kernel is deprecated together):
- NELocallyConnectedLayer
- NELocallyConnectedMatrixMultiplyKernel
- NEAbsoluteDifference
@@ -449,7 +449,7 @@ v20.08 Public major release
- @ref CLScaleKernel
- New OpenCL kernels / functions:
- @ref CLMaxUnpoolingLayerKernel
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- @ref NEMaxUnpoolingLayerKernel
- New graph example:
- graph_yolov3_output_detector
@@ -485,7 +485,7 @@ v20.08 Public major release
- Removed OpenCL kernels / functions:
- CLGEMMLowpQuantizeDownInt32ToUint8Scale
- CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFloat
- - Removed NEON kernels / functions:
+ - Removed Neon kernels / functions:
- NEGEMMLowpQuantizeDownInt32ToUint8Scale
- NEGEMMMatrixAccumulateBiasesKernel
- Deprecated functions / interfaces:
@@ -551,7 +551,7 @@ v20.05 Public major release
- New OpenCL kernels / functions:
- @ref CLQLSTMLayer
- @ref CLQLSTMLayerNormalizationKernel
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- @ref NEQLSTMLayer
- @ref NEQLSTMLayerNormalizationKernel
- Added HARD_SWISH support in:
@@ -560,20 +560,20 @@ v20.05 Public major release
- Deprecated OpenCL kernels / functions:
- CLGEMMLowpQuantizeDownInt32ToUint8Scale
- CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFloat
- - Deprecated NEON kernels / functions:
+ - Deprecated Neon kernels / functions:
- NEGEMMLowpQuantizeDownInt32ToUint8Scale
- Removed CPP kernels / functions:
- CPPFlipWeightsKernel
- Removed PoolingLayerInfo constructors without Data Layout.
- Removed CLDepthwiseConvolutionLayer3x3
- Removed NEDepthwiseConvolutionLayerOptimized
- - Added support for Winograd 3x3,4x4 on NEON FP16:
+ - Added support for Winograd 3x3,4x4 on Neon FP16:
- @ref NEWinogradConvolutionLayer
- @ref NEWinogradLayerTransformInputKernel
- @ref NEWinogradLayerTransformOutputKernel
- @ref NEWinogradLayerTransformWeightsKernel
- Added CLCompileContext
- - Added NEON GEMM kernel with 2D window support
+ - Added Neon GEMM kernel with 2D window support
v20.02.1 Maintenance release
- Added Android-NN build script.
@@ -611,14 +611,14 @@ v20.02 Public major release
- New OpenCL kernels / functions:
- @ref CLFill
- CLGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel / @ref CLGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPoint
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- @ref NEFill
- @ref NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel / @ref NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPoint
- - Deprecated NEON functions / interfaces:
+ - Deprecated Neon functions / interfaces:
- CLDepthwiseConvolutionLayer3x3
- NEDepthwiseConvolutionLayerOptimized
- PoolingLayerInfo constructors without Data Layout.
- - Added support for quantization with multiplier greater than 1 on NEON and CL.
+ - Added support for quantization with multiplier greater than 1 on Neon and CL.
- Added support for quantized inputs of type QASYMM8_SIGNED and QASYMM8 to @ref CLQuantizationLayer.
- Added the ability to build bootcode for bare metal.
- Added support for generating synthetic QASYMM8 graphs.
@@ -643,7 +643,7 @@ v19.11 Public major release
- CLDepthwiseSeparableConvolutionLayer
- CLDepthwiseVectorToTensorKernel
- CLDirectConvolutionLayerOutputStageKernel
- - Deprecated NEON kernels / functions:
+ - Deprecated Neon kernels / functions:
- NEDepthwiseWeightsReshapeKernel
- NEDepthwiseIm2ColKernel
- NEDepthwiseSeparableConvolutionLayer
@@ -654,7 +654,7 @@ v19.11 Public major release
- @ref CLDepthwiseConvolutionLayerNativeKernel to replace the old generic depthwise convolution (see Deprecated
OpenCL kernels / functions)
- @ref CLLogSoftmaxLayer
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- @ref NEBoundingBoxTransformKernel / @ref NEBoundingBoxTransform
- @ref NEComputeAllAnchorsKernel / NEComputeAllAnchors
- @ref NEDetectionPostProcessLayer
@@ -693,8 +693,8 @@ v19.11 Public major release
- Replaced the calls to CLCopyKernel and CLMemsetKernel with @ref CLPadLayer in @ref CLGenerateProposalsLayer.
- Improved performance for CL Inception V3 - FP16.
- Improved accuracy for CL Inception V3 - FP16 by enabling FP32 accumulator (mixed-precision).
- - Improved NEON performance by enabling fusing batch normalization with convolution and depth-wise convolution layer.
- - Improved NEON performance for MobileNet-SSD by improving the output detection performance.
+ - Improved Neon performance by enabling fusing batch normalization with convolution and depth-wise convolution layer.
+ - Improved Neon performance for MobileNet-SSD by improving the output detection performance.
- Optimized @ref CLPadLayer.
- Optimized CL generic depthwise convolution layer by introducing @ref CLDepthwiseConvolutionLayerNativeKernel.
- Reduced memory consumption by implementing weights sharing.
@@ -710,7 +710,7 @@ v19.08.1 Public maintenance release
v19.08 Public major release
- Various bug fixes.
- Various optimisations.
- - Deprecated NEON functions
+ - Deprecated Neon functions
- NEDepthConcatenateLayer
- NEWidthConcatenateLayer
- Deprecated OpenCL kernels / functions
@@ -718,7 +718,7 @@ v19.08 Public major release
- CLGEMMInterleave4x4Kernel / CLGEMMInterleave4x4
- CLGEMMTranspose1xWKernel / CLGEMMTranspose1xW
- CLWidthConcatenateLayer
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- @ref NEAbsLayer
- @ref NECast
- @ref NEElementwisePower
@@ -757,15 +757,15 @@ v19.08 Public major release
- Added support for REDUCE_MIN and REDUCE_MAX in @ref ReductionOperation
- Enable the fusion of batch normalization with convolution and depthwise convolution layer for FP32 in the graph API (OpenCL only)
- Added support for fusing activation function and broadcast addition with the matrix multiplication for FP32 (OpenCL only)
- - Re-factored the depthwise convolution layer kernel on NEON for generic cases
- - Added an optimized depthwise convolution layer kernel for 5x5 filters (NEON only)
+ - Re-factored the depthwise convolution layer kernel on Neon for generic cases
+ - Added an optimized depthwise convolution layer kernel for 5x5 filters (Neon only)
- Added support to enable OpenCL kernel cache. Added example showing how to load the prebuilt OpenCL kernels from a binary cache file
- Altered @ref QuantizationInfo interface to support per-channel quantization.
- The CLDepthwiseConvolutionLayer3x3 will be included by @ref CLDepthwiseConvolutionLayer to accommodate for future optimizations.
- The NEDepthwiseConvolutionLayerOptimized will be included by @ref NEDepthwiseConvolutionLayer to accommodate for future optimizations.
- Removed inner_border_right and inner_border_top parameters from @ref CLDeconvolutionLayer interface
- Removed inner_border_right and inner_border_top parameters from @ref NEDeconvolutionLayer interface
- - Optimized the NEON assembly kernel for GEMMLowp. The new implementation fuses the output stage and quantization with the matrix multiplication kernel
+ - Optimized the Neon assembly kernel for GEMMLowp. The new implementation fuses the output stage and quantization with the matrix multiplication kernel
v19.05 Public major release
- Various bug fixes.
@@ -822,7 +822,7 @@ v19.05 Public major release
- Add support for QASYMM8 in NEArithmeticSubtractionKernel.
- Add support for QASYMM8 in NEPixelWiseMultiplicationKernel.
- Add support for QASYMM8 NEDeconvolution.
- - Add support for DequantizationLayer for NEON/CL.
+ - Add support for DequantizationLayer for Neon/CL.
- Add support for dilation in CLDepthwiseConvolution.
- Fuse offset contribution with the output stage when we use NEGEMMLowpMatrixMultiplyCore.
- Optimize CLDeconvolution.
@@ -898,7 +898,7 @@ v19.02 Public major release
- @ref NESoftmaxLayer
- Fused activation in @ref CLWinogradConvolutionLayer
- Extented @ref NEPermute to support more cases
- - Added NEON/SVE GEMM Hybrid kernels
+ - Added Neon/SVE GEMM Hybrid kernels
- Added u8 and s8 hybrid assembly kernels
- Introduced GEMM strategy name in NEGEMMAssemblyWrapper
- Improved @ref CLTuner
@@ -1012,7 +1012,7 @@ v18.05 Public major release
- Removed arm_compute::NEGEMMLowpAArch64A53Kernel / arm_compute::NEGEMMLowpAArch64Kernel / arm_compute::NEGEMMLowpAArch64V8P4Kernel / arm_compute::NEGEMMInterleavedBlockedKernel / arm_compute::NEGEMMLowpAssemblyMatrixMultiplyCore / arm_compute::NEHGEMMAArch64FP16Kernel
- Added NEGEMMAssemblyWrapper and AssemblyKernelGlue which are used to execute assembly kernels in neon functions.
- Minor changes to the CPUInfo type to make it compatible with the new assembly gemm interface.
- - Moved neon assembly kernels to the folder src/core/NEON/kernels/arm_gemm.
+ - Moved neon assembly kernels to the folder src/core/Neon/kernels/arm_gemm.
- Improved doxygen documentation.
- Improved memory management for layer's transitions.
- Added support for NHWC data layout in tensors.
@@ -1043,7 +1043,7 @@ v18.05 Public major release
- Port mobilenet example to NHWC data layout.
- Enabled Winograd method in @ref CLConvolutionLayer.
- Renamed NEWinogradLayer to @ref NEWinogradConvolutionLayer.
- - Updated @ref NEWinogradConvolutionLayer to use highly optimised assembly kernels in src/core/NEON/kernels/arm_gemm.
+ - Updated @ref NEWinogradConvolutionLayer to use highly optimised assembly kernels in src/core/Neon/kernels/arm_gemm.
- Added memory manager support in GLES functions.
- Major refactoring of the graph API.
- Added GLES backend in the graph API.
@@ -1053,7 +1053,7 @@ v18.05 Public major release
- Replaced NEDeconvolutionLayerUpsampleKernel with @ref NEScaleKernel in @ref NEDeconvolutionLayer.
- Added fast maths flag in @ref CLConvolutionLayer.
- Added new tests and benchmarks in validation and benchmark frameworks
- - Merge Activation layer with Convolution Layer (NEON. CL, GLES)
+ - Merge Activation layer with Convolution Layer (Neon. CL, GLES)
- Added support to OpenCL 2.0 SVM
- Added support to import memory in OpenCL tensors.
- Added the prepare() method to perform any one off pre-processing before running the function.
@@ -1072,7 +1072,7 @@ v18.03 Public maintenance release
- Renamed NEWinogradLayer.cpp to @ref NEWinogradConvolutionLayer
v18.02 Public major release
- - Various NEON / OpenCL / GLES optimisations.
+ - Various Neon / OpenCL / GLES optimisations.
- Various bug fixes.
- Changed default number of threads on big LITTLE systems.
- Refactored examples and added:
@@ -1097,7 +1097,7 @@ v18.02 Public major release
- Added support for non-square pooling to @ref NEPoolingLayer and @ref CLPoolingLayer
- New OpenCL kernels / functions:
- CLDirectConvolutionLayerOutputStageKernel
- - New NEON kernels / functions
+ - New Neon kernels / functions
- Added name() method to all kernels.
- Added support for Winograd 5x5.
- NEPermuteKernel / @ref NEPermute
@@ -1124,9 +1124,9 @@ v18.01 Public maintenance release
- @ref GCGEMMInterleave4x4Kernel
- @ref GCGEMMTranspose1xWKernel
- @ref GCIm2ColKernel
- - Refactored NEON Winograd (NEWinogradLayerKernel)
+ - Refactored Neon Winograd (NEWinogradLayerKernel)
- Added @ref NEDirectConvolutionLayerOutputStageKernel
- - Added QASYMM8 support to the following NEON kernels:
+ - Added QASYMM8 support to the following Neon kernels:
- NEDepthwiseConvolutionLayer3x3Kernel
- @ref NEFillBorderKernel
- NEPoolingLayerKernel
@@ -1141,7 +1141,7 @@ v17.12 Public major release
- Introduced logging interface
- Introduced opencl timer
- Reworked GEMMLowp interface
- - Added new NEON assembly kernels for GEMMLowp, SGEMM and HGEMM
+ - Added new Neon assembly kernels for GEMMLowp, SGEMM and HGEMM
- Added validation method for most Machine Learning kernels / functions
- Added new graph examples such as googlenet, mobilenet, squeezenet, vgg16 and vgg19
- Added sgemm example for OpenCL
@@ -1168,7 +1168,7 @@ v17.12 Public major release
- @ref GCLogits1DMaxKernel / @ref GCLogits1DShiftExpSumKernel / @ref GCLogits1DNormKernel / @ref GCSoftmaxLayer
- @ref GCTransposeKernel / @ref GCTranspose
- - New NEON kernels / functions
+ - New Neon kernels / functions
- arm_compute::NEGEMMLowpAArch64A53Kernel / arm_compute::NEGEMMLowpAArch64Kernel / arm_compute::NEGEMMLowpAArch64V8P4Kernel / arm_compute::NEGEMMInterleavedBlockedKernel / arm_compute::NEGEMMLowpAssemblyMatrixMultiplyCore
- arm_compute::NEHGEMMAArch64FP16Kernel
- NEDepthwiseConvolutionLayer3x3Kernel / NEDepthwiseIm2ColKernel / NEGEMMMatrixVectorMultiplyKernel / NEDepthwiseVectorToTensorKernel / @ref NEDepthwiseConvolutionLayer
@@ -1180,7 +1180,7 @@ v17.12 Public major release
- @ref CLGEMMLowpOffsetContributionKernel / @ref CLGEMMLowpMatrixAReductionKernel / @ref CLGEMMLowpMatrixBReductionKernel / @ref CLGEMMLowpMatrixMultiplyCore
- CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel / @ref CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPoint
- - New graph nodes for NEON and OpenCL
+ - New graph nodes for Neon and OpenCL
- graph::BranchLayer
- graph::DepthConvertLayer
- graph::DepthwiseConvolutionLayer
@@ -1204,8 +1204,8 @@ v17.09 Public major release
- Experimental Graph support: initial implementation of a simple stream API to easily chain machine learning layers.
- Memory Manager (@ref BlobLifetimeManager, @ref BlobMemoryPool, @ref ILifetimeManager, @ref IMemoryGroup, @ref IMemoryManager, @ref IMemoryPool, @ref IPoolManager, @ref MemoryManagerOnDemand, @ref PoolManager)
- New validation and benchmark frameworks (Boost and Google frameworks replaced by homemade framework).
- - Most machine learning functions support both fixed point 8 and 16 bit (QS8, QS16) for both NEON and OpenCL.
- - New NEON kernels / functions:
+ - Most machine learning functions support both fixed point 8 and 16 bit (QS8, QS16) for both Neon and OpenCL.
+ - New Neon kernels / functions:
- arm_compute::NEGEMMAssemblyBaseKernel arm_compute::NEGEMMAArch64Kernel
- @ref NEDequantizationLayerKernel / @ref NEDequantizationLayer
- NEFloorKernel / @ref NEFloor
@@ -1231,12 +1231,12 @@ v17.09 Public major release
v17.06 Public major release
- Various bug fixes
- - Added support for fixed point 8 bit (QS8) to the various NEON machine learning kernels.
+ - Added support for fixed point 8 bit (QS8) to the various Neon machine learning kernels.
- Added unit tests and benchmarks (AlexNet, LeNet)
- Added support for sub tensors.
- Added infrastructure to provide GPU specific optimisation for some OpenCL kernels.
- - Added @ref OMPScheduler (OpenMP) scheduler for NEON
- - Added @ref SingleThreadScheduler scheduler for NEON (For bare metal)
+ - Added @ref OMPScheduler (OpenMP) scheduler for Neon
+ - Added @ref SingleThreadScheduler scheduler for Neon (For bare metal)
- User can specify his own scheduler by implementing the @ref IScheduler interface.
- New OpenCL kernels / functions:
- @ref CLBatchNormalizationLayerKernel / @ref CLBatchNormalizationLayer
@@ -1246,7 +1246,7 @@ v17.06 Public major release
- @ref CLWeightsReshapeKernel / @ref CLConvolutionLayerReshapeWeights
- New C++ kernels:
- @ref CPPDetectionWindowNonMaximaSuppressionKernel
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- @ref NEBatchNormalizationLayerKernel / @ref NEBatchNormalizationLayer
- NEDepthConcatenateLayerKernel / NEDepthConcatenateLayer
- @ref NEDirectConvolutionLayerKernel / @ref NEDirectConvolutionLayer
@@ -1284,11 +1284,11 @@ v17.04 Public bug fixes release
v17.03.1 First Major public release of the sources
- Renamed the library to arm_compute
- - New CPP target introduced for C++ kernels shared between NEON and CL functions.
+ - New CPP target introduced for C++ kernels shared between Neon and CL functions.
- New padding calculation interface introduced and ported most kernels / functions to use it.
- New OpenCL kernels / functions:
- CLGEMMLowpMatrixMultiplyKernel / CLGEMMLowp
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- @ref NENormalizationLayerKernel / @ref NENormalizationLayer
- @ref NETransposeKernel / @ref NETranspose
- NELogits1DMaxKernel, NELogits1DShiftExpSumKernel, NELogits1DNormKernel / @ref NESoftmaxLayer
@@ -1305,7 +1305,7 @@ v17.03 Sources preview
- @ref CLLKTrackerInitKernel, @ref CLLKTrackerStage0Kernel, @ref CLLKTrackerStage1Kernel, @ref CLLKTrackerFinalizeKernel / @ref CLOpticalFlow
- @ref CLNormalizationLayerKernel / @ref CLNormalizationLayer
- @ref CLLaplacianPyramid, @ref CLLaplacianReconstruct
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- NEActivationLayerKernel / @ref NEActivationLayer
- GEMM refactoring + FP16 support (Requires armv8.2 CPU): @ref NEGEMMInterleave4x4Kernel, @ref NEGEMMTranspose1xWKernel, @ref NEGEMMMatrixMultiplyKernel, @ref NEGEMMMatrixAdditionKernel / @ref NEGEMM
- NEPoolingLayerKernel / @ref NEPoolingLayer
@@ -1319,7 +1319,7 @@ v17.02.1 Sources preview
- @ref CLGaussianPyramidHorKernel, @ref CLGaussianPyramidVertKernel / @ref CLGaussianPyramid, @ref CLGaussianPyramidHalf, @ref CLGaussianPyramidOrb
- @ref CLMinMaxKernel, @ref CLMinMaxLocationKernel / @ref CLMinMaxLocation
- @ref CLNonLinearFilterKernel / @ref CLNonLinearFilter
- - New NEON FP16 kernels (Requires armv8.2 CPU)
+ - New Neon FP16 kernels (Requires armv8.2 CPU)
- @ref NEAccumulateWeightedFP16Kernel
- @ref NEBox3x3FP16Kernel
- @ref NENonMaximaSuppression3x3FP16Kernel
@@ -1331,7 +1331,7 @@ v17.02 Sources preview
- @ref CLDerivativeKernel / @ref CLChannelExtract
- @ref CLFastCornersKernel / @ref CLFastCorners
- @ref CLMeanStdDevKernel / @ref CLMeanStdDev
- - New NEON kernels / functions:
+ - New Neon kernels / functions:
- HOG / SVM: @ref NEHOGOrientationBinningKernel, @ref NEHOGBlockNormalizationKernel, @ref NEHOGDetectorKernel, NEHOGNonMaximaSuppressionKernel / @ref NEHOGDescriptor, @ref NEHOGDetector, @ref NEHOGGradient, @ref NEHOGMultiDetection
- @ref NENonLinearFilterKernel / @ref NENonLinearFilter
- Introduced a CLScheduler to manage the default context and command queue used by the runtime library and create synchronisation events.
@@ -1524,11 +1524,11 @@ To see the build options available simply run ```scons -h```:
@b arch: The x86_32 and x86_64 targets can only be used with neon=0 and opencl=1.
@b os: Choose the operating system you are targeting: Linux, Android or bare metal.
-@note bare metal can only be used for NEON (not OpenCL), only static libraries get built and NEON's multi-threading support is disabled.
+@note bare metal can only be used for Neon (not OpenCL), only static libraries get built and Neon's multi-threading support is disabled.
@b build: you can either build directly on your device (native) or cross compile from your desktop machine (cross-compile). In both cases make sure the compiler is available in your path.
-@note If you want to natively compile for 32bit on a 64bit ARM device running a 64bit OS then you will have to use cross-compile too.
+@note If you want to natively compile for 32bit on a 64bit Arm device running a 64bit OS then you will have to use cross-compile too.
There is also an 'embed_only' option which will generate all the .embed files for the OpenCL kernels and / or OpenGLES compute shaders. This might be useful if using a different build system to compile the library.
@@ -1536,7 +1536,7 @@ In addittion the option 'compress_kernels' will compress the embedded OpenCL ker
@b Werror: If you are compiling using the same toolchains as the ones used in this guide then there shouldn't be any warning and therefore you should be able to keep Werror=1. If with a different compiler version the library fails to build because of warnings interpreted as errors then, if you are sure the warnings are not important, you might want to try to build with Werror=0 (But please do report the issue on Github).
-@b opencl / @b neon / @b gles_compute: Choose which SIMD technology you want to target. (NEON for ARM Cortex-A CPUs or OpenCL / GLES_COMPUTE for ARM Mali GPUs)
+@b opencl / @b neon / @b gles_compute: Choose which SIMD technology you want to target. (Neon for Arm Cortex-A CPUs or OpenCL / GLES_COMPUTE for Arm Mali GPUs)
@b embed_kernels: For OpenCL / GLES_COMPUTE only: set embed_kernels=1 if you want the OpenCL / GLES_COMPUTE kernels to be built in the library's binaries instead of being read from separate ".cl" / ".cs" files. If embed_kernels is set to 0 then the application can set the path to the folder containing the OpenCL / GLES_COMPUTE kernel files by calling CLKernelLibrary::init() / GCKernelLibrary::init(). By default the path is set to "./cl_kernels" / "./cs_shaders".
@@ -1564,11 +1564,11 @@ Example:
@b mali: Enable the collection of Mali hardware counters to measure execution time in benchmark tests. (Your device needs to have a Mali driver that supports it)
-@b openmp Build in the OpenMP scheduler for NEON.
+@b openmp Build in the OpenMP scheduler for Neon.
@note Only works when building with g++ not clang++
-@b cppthreads Build in the C++11 scheduler for NEON.
+@b cppthreads Build in the C++11 scheduler for Neon.
@sa Scheduler::set
@@ -1582,12 +1582,12 @@ In order to use this option, the external tests directory must have the followin
│   ├── CL
│   ├── datasets
│   ├── fixtures
- │   └── NEON
+ │   └── Neon
└── validation
   ├── CL
    ├── datasets
    ├── fixtures
-     └── NEON
+     └── Neon
Then, build the library with `external_tests_dir=<PATH_TO_EXTERNAL_TESTS_DIR>`.
@@ -1600,7 +1600,7 @@ For Linux, the library was successfully built and tested using the following Lin
- gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf
- gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu
-To cross-compile the library in debug mode, with NEON only support, for Linux 32bit:
+To cross-compile the library in debug mode, with Neon only support, for Linux 32bit:
scons Werror=1 -j8 debug=1 neon=1 opencl=0 os=linux arch=armv7a
@@ -1612,12 +1612,12 @@ To cross-compile the library in asserts mode, with GLES_COMPUTE only support, fo
scons Werror=1 -j8 debug=0 asserts=1 neon=0 opencl=0 gles_compute=1 embed_kernels=1 os=linux arch=arm64-v8a
-You can also compile the library natively on an ARM device by using <b>build=native</b>:
+You can also compile the library natively on an Arm device by using <b>build=native</b>:
scons Werror=1 -j8 debug=0 neon=1 opencl=0 os=linux arch=arm64-v8a build=native
scons Werror=1 -j8 debug=0 neon=1 opencl=0 os=linux arch=armv7a build=native
-@note g++ for ARM is mono-arch, therefore if you want to compile for Linux 32bit on a Linux 64bit platform you will have to use a cross compiler.
+@note g++ for Arm is mono-arch, therefore if you want to compile for Linux 32bit on a Linux 64bit platform you will have to use a cross compiler.
For example on a 64bit Debian based system you would have to install <b>g++-arm-linux-gnueabihf</b>
@@ -1637,11 +1637,11 @@ The examples get automatically built by scons as part of the build process of th
@note The following command lines assume the arm_compute libraries are present in the current directory or in the system library path. If this is not the case you can specify the location of the pre-built libraries with the compiler option -L. When building the OpenCL example the commands below assume that the CL headers are located in the include folder where the command is executed.
-To cross compile a NEON example for Linux 32bit:
+To cross compile a Neon example for Linux 32bit:
arm-linux-gnueabihf-g++ examples/neon_convolution.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -mfpu=neon -L. -larm_compute -larm_compute_core -o neon_convolution
-To cross compile a NEON example for Linux 64bit:
+To cross compile a Neon example for Linux 64bit:
aarch64-linux-gnu-g++ examples/neon_convolution.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -L. -larm_compute -larm_compute_core -o neon_convolution
@@ -1679,21 +1679,21 @@ i.e. to cross compile the "graph_lenet" example for Linux 64bit:
@note If compiling using static libraries, this order must be followed when linking: arm_compute_graph_static, arm_compute, arm_compute_core
-To compile natively (i.e directly on an ARM device) for NEON for Linux 32bit:
+To compile natively (i.e directly on an Arm device) for Neon for Linux 32bit:
g++ examples/neon_convolution.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -mfpu=neon -larm_compute -larm_compute_core -o neon_convolution
-To compile natively (i.e directly on an ARM device) for NEON for Linux 64bit:
+To compile natively (i.e directly on an Arm device) for Neon for Linux 64bit:
g++ examples/neon_convolution.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute -larm_compute_core -o neon_convolution
(notice the only difference with the 32 bit command is that we don't need the -mfpu option)
-To compile natively (i.e directly on an ARM device) for OpenCL for Linux 32bit or Linux 64bit:
+To compile natively (i.e directly on an Arm device) for OpenCL for Linux 32bit or Linux 64bit:
g++ examples/cl_convolution.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute -larm_compute_core -o cl_convolution -DARM_COMPUTE_CL
-To compile natively (i.e directly on an ARM device) for GLES for Linux 32bit or Linux 64bit:
+To compile natively (i.e directly on an Arm device) for GLES for Linux 32bit or Linux 64bit:
g++ examples/gc_absdiff.cpp utils/Utils.cpp -I. -Iinclude/ -L. -larm_compute -larm_compute_core -std=c++14 -DARM_COMPUTE_GC -Iinclude/linux/ -o gc_absdiff
@@ -1768,7 +1768,7 @@ Here is a guide to <a href="https://developer.android.com/ndk/guides/standalone_
@subsubsection S3_3_1_library How to build the library ?
-To cross-compile the library in debug mode, with NEON only support, for Android 32bit:
+To cross-compile the library in debug mode, with Neon only support, for Android 32bit:
CXX=clang++ CC=clang scons Werror=1 -j8 debug=1 neon=1 opencl=0 os=android arch=armv7a
@@ -1788,7 +1788,7 @@ The examples get automatically built by scons as part of the build process of th
Once you've got your Android standalone toolchain built and added to your path you can do the following:
-To cross compile a NEON example:
+To cross compile a Neon example:
#32 bit:
arm-linux-androideabi-clang++ examples/neon_convolution.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute-static -larm_compute_core-static -L. -o neon_convolution_arm -static-libstdc++ -pie
@@ -1850,7 +1850,7 @@ And finally to run the example:
For example:
adb shell /data/local/tmp/graph_lenet --help
-In this case the first argument of LeNet (like all the graph examples) is the target (i.e 0 to run on NEON, 1 to run on OpenCL if available, 2 to run on OpenCL using the CLTuner), the second argument is the path to the folder containing the npy files for the weights and finally the third argument is the number of batches to run.
+In this case the first argument of LeNet (like all the graph examples) is the target (i.e 0 to run on Neon, 1 to run on OpenCL if available, 2 to run on OpenCL using the CLTuner), the second argument is the path to the folder containing the npy files for the weights and finally the third argument is the number of batches to run.
@subsection S3_4_macos Building for macOS
@@ -1874,7 +1874,7 @@ Download linaro for <a href="https://releases.linaro.org/components/toolchain/bi
@subsubsection S3_5_1_library How to build the library ?
-To cross-compile the library with NEON support for baremetal arm64-v8a:
+To cross-compile the library with Neon support for baremetal arm64-v8a:
scons Werror=1 -j8 debug=0 neon=1 opencl=0 os=bare_metal arch=arm64-v8a build=cross_compile cppthreads=0 openmp=0 standalone=1
diff --git a/docs/01_library.dox b/docs/01_library.dox
index 742a246582..848b060e9f 100644
--- a/docs/01_library.dox
+++ b/docs/01_library.dox
@@ -38,10 +38,10 @@ The Core library is a low level collection of algorithms implementations, it is
The Runtime library is a very basic wrapper around the Core library which can be used for quick prototyping, it is basic in the sense that:
- It allocates images and tensors by using standard malloc().
-- It multi-threads NEON code in a very basic way using a very simple pool of threads.
+- It multi-threads Neon code in a very basic way using a very simple pool of threads.
- For OpenCL it uses the default CLScheduler command queue for all mapping operations and kernels.
-For maximum performance, it is expected that the users would re-implement an equivalent to the runtime library which suits better their needs (With a more clever multi-threading strategy, load-balancing between NEON and OpenCL, etc.)
+For maximum performance, it is expected that the users would re-implement an equivalent to the runtime library which suits better their needs (With a more clever multi-threading strategy, load-balancing between Neon and OpenCL, etc.)
@section S4_1_2 Data-type and Data-layout support
@@ -62,7 +62,7 @@ where N = batches, C = channels, H = height, W = width
@section S4_1_3 Fast-math support
Compute Library supports different types of convolution methods, fast-math flag is only used for the Winograd algorithm.
-When the fast-math flag is enabled, both NEON and CL convolution layers will try to dispatch the fastest implementation available, which may introduce a drop in accuracy as well. The different scenarios involving the fast-math flag are presented below:
+When the fast-math flag is enabled, both Neon and CL convolution layers will try to dispatch the fastest implementation available, which may introduce a drop in accuracy as well. The different scenarios involving the fast-math flag are presented below:
- For FP32:
- no-fast-math: Only supports Winograd 3x3,3x1,1x3,5x1,1x5,7x1,1x7
- fast-math: Supports Winograd 3x3,3x1,1x3,5x1,1x5,7x1,1x7,5x5,7x7
@@ -116,7 +116,7 @@ kernel.run( q, max_window ); // Enqueue the kernel to process the full window on
q.finish();
@endcode
-NEON / CPP kernels:
+Neon / CPP kernels:
@code{.cpp}
//Create a kernel object:
@@ -131,7 +131,7 @@ kernel.run( max_window ); // Run the kernel on the full window
@subsection S4_2_3 Multi-threading
-The previous section shows how to run a NEON / CPP kernel in the current thread, however if your system has several CPU cores, you will probably want the kernel to use several cores. Here is how this can be done:
+The previous section shows how to run a Neon / CPP kernel in the current thread, however if your system has several CPU cores, you will probably want the kernel to use several cores. Here is how this can be done:
@code{.cpp}
ThreadInfo info;
@@ -181,7 +181,7 @@ The previous section shows how to run a NEON / CPP kernel in the current thread,
}
@endcode
-This is a very basic implementation which was originally used in the NEON runtime library by all the NEON functions.
+This is a very basic implementation which was originally used in the Neon runtime library by all the Neon functions.
@sa CPPScheduler
@@ -228,11 +228,11 @@ In order to block until all the jobs in the CLScheduler's command queue are done
For example:
@snippet cl_events.cpp OpenCL events
-@subsection S4_4_2_cl_neon OpenCL / NEON interoperability
+@subsection S4_4_2_cl_neon OpenCL / Neon interoperability
-You can mix OpenCL and NEON kernels and functions. However it is the user's responsibility to handle the mapping/unmapping of OpenCL objects, for example:
+You can mix OpenCL and Neon kernels and functions. However it is the user's responsibility to handle the mapping/unmapping of OpenCL objects, for example:
-@snippet neoncl_scale_median_gaussian.cpp NEON / OpenCL Interop
+@snippet neoncl_scale_median_gaussian.cpp Neon / OpenCL Interop
@sa main_neoncl_scale_median_gaussian
@@ -256,7 +256,7 @@ You have 3 types of @ref BorderMode :
- @ref BorderMode::REPLICATE : Neighbor pixels outside of the image are treated as having the same value as the closest valid pixel.
- @ref BorderMode::CONSTANT : Neighbor pixels outside of the image are treated as having the same constant value. (The user can choose what this value should be).
-Moreover both OpenCL and NEON use vector loads and stores instructions to access the data in buffers, so in order to avoid having special cases to handle for the borders all the images and tensors used in this library must be padded.
+Moreover both OpenCL and Neon use vector loads and stores instructions to access the data in buffers, so in order to avoid having special cases to handle for the borders all the images and tensors used in this library must be padded.
@subsubsection padding Padding
@@ -483,7 +483,7 @@ conv2.run();
The implemented @ref TensorAllocator and @ref CLTensorAllocator objects provide an interface capable of importing existing memory to a tensor as backing memory.
-A simple NEON example can be the following:
+A simple Neon example can be the following:
@code{.cpp}
// External backing memory
void* external_ptr = ...;
@@ -550,6 +550,6 @@ Consequently, this will allow finer control of these services among pipelines wh
This feature introduces some changes to our API.
All the kernels/functions will now accept a Runtime Context object which will allow the function to use the mentioned services.
-Finally, we will try to adapt our code-base progressively to use the new mechanism but will continue supporting the legacy mechanism to allow a smooth transition. Changes will apply to all our three backends: NEON, OpenCL and OpenGL ES.
+Finally, we will try to adapt our code-base progressively to use the new mechanism but will continue supporting the legacy mechanism to allow a smooth transition. Changes will apply to all our three backends: Neon, OpenCL and OpenGL ES.
*/
} // namespace arm_compute
diff --git a/docs/02_tests.dox b/docs/02_tests.dox
index c46e1f5663..0aee8e59d8 100644
--- a/docs/02_tests.dox
+++ b/docs/02_tests.dox
@@ -371,7 +371,7 @@ To run the OpenCL precommit validation tests:
LD_LIBRARY_PATH=. ./arm_compute_validation --mode=precommit --filter="^CL.*"
-To run the NEON precommit benchmark tests with PMU and Wall Clock timer in miliseconds instruments enabled:
+To run the Neon precommit benchmark tests with PMU and Wall Clock timer in miliseconds instruments enabled:
LD_LIBRARY_PATH=. ./arm_compute_benchmark --mode=precommit --filter="^NEON.*" --instruments="pmu,wall_clock_timer_ms" --iterations=10
diff --git a/docs/04_adding_operator.dox b/docs/04_adding_operator.dox
index f311fb4d51..1b4b575964 100644
--- a/docs/04_adding_operator.dox
+++ b/docs/04_adding_operator.dox
@@ -71,12 +71,12 @@ Similarly, all common functions that process shapes, like calculating output sha
@subsection S4_1_2_add_kernel Add a kernel
-As we mentioned at the beginning, the kernel is the implementation of the operator or algorithm partially using a specific programming language related to the backend we want to use. Adding a kernel in the library means implementing the algorithm in a SIMD technology like NEON or OpenCL. All kernels in Compute Library must implement a common interface IKernel or one of the specific subinterfaces.
+As we mentioned at the beginning, the kernel is the implementation of the operator or algorithm partially using a specific programming language related to the backend we want to use. Adding a kernel in the library means implementing the algorithm in a SIMD technology like Neon or OpenCL. All kernels in Compute Library must implement a common interface IKernel or one of the specific subinterfaces.
IKernel is the common interface for all the kernels in the core library, it contains the main methods for configure and run the kernel itself, such as window() that return the maximum window the kernel can be executed on or is_parallelisable() for indicate whether or not the kernel is parallelizable. If the kernel is parallelizable then the window returned by the window() method can be split into sub-windows which can then be run in parallel, in the other case, only the window returned by window() can be passed to the run method.
There are specific interfaces for OpenCL and Neon: @ref ICLKernel, INEKernel (using INEKernel = @ref ICPPKernel).
- @ref ICLKernel is the common interface for all the OpenCL kernels. It implements the inherited methods and adds all the methods necessary to configure the CL kernel, such as set/return the Local-Workgroup-Size hint, add single, array or tensor argument, set the targeted GPU architecture according to the CL device. All these methods are used during the configuration and the run of the operator.
-- INEKernel inherits from @ref IKernel as well and it's the common interface for all kernels implemented in NEON, it adds just the run and the name methods.
+- INEKernel inherits from @ref IKernel as well and it's the common interface for all kernels implemented in Neon, it adds just the run and the name methods.
There are two others implementation of @ref IKernel called @ref ICLSimpleKernel and INESimpleKernel, they are the interface for simple kernels that have just one input tensor and one output tensor.
Creating a new kernel implies adding new files:
@@ -120,10 +120,10 @@ For OpenCL:
@snippet src/core/gpu/cl/kernels/ClReshapeKernel.cpp ClReshapeKernel Kernel
The run will call the function defined in the .cl file.
-For the NEON backend case:
+For the Neon backend case:
@snippet src/core/cpu/kernels/CpuReshapeKernel.cpp NEReshapeLayerKernel Kernel
-In the NEON case, there is no need to add an extra file and we implement the kernel in the same NEReshapeLayerKernel.cpp file.
+In the Neon case, there is no need to add an extra file and we implement the kernel in the same NEReshapeLayerKernel.cpp file.
If the tests are already in place, the new kernel can be tested using the existing tests by adding the configure and run of the kernel to the compute_target() in the fixture.
@@ -137,13 +137,13 @@ If the tests are already in place, the new kernel can be tested using the existi
- (sub[n].start() - max[n].start()) % max[n].step() == 0
- (sub[n].end() - sub[n].start()) % max[n].step() == 0
-@ref CPPScheduler::schedule provides a sample implementation that is used for NEON kernels.
-%Memory management is the other aspect that the runtime layer is supposed to handle. %Memory management of the tensors is abstracted using TensorAllocator. Each tensor holds a pointer to a TensorAllocator object, which is used to allocate and free the memory at runtime. The implementation that is currently supported in Compute Library allows memory blocks, required to be fulfilled for a given operator, to be grouped together under a @ref MemoryGroup. Each group can be acquired and released. The underlying implementation of memory groups vary depending on whether NEON or CL is used. The memory group class uses memory pool to provide the required memory. It also uses the memory manager to manage the lifetime and a IPoolManager to manage the memory pools registered with the memory manager.
+@ref CPPScheduler::schedule provides a sample implementation that is used for Neon kernels.
+%Memory management is the other aspect that the runtime layer is supposed to handle. %Memory management of the tensors is abstracted using TensorAllocator. Each tensor holds a pointer to a TensorAllocator object, which is used to allocate and free the memory at runtime. The implementation that is currently supported in Compute Library allows memory blocks, required to be fulfilled for a given operator, to be grouped together under a @ref MemoryGroup. Each group can be acquired and released. The underlying implementation of memory groups vary depending on whether Neon or CL is used. The memory group class uses memory pool to provide the required memory. It also uses the memory manager to manage the lifetime and a IPoolManager to manage the memory pools registered with the memory manager.
We have seen the various interfaces for a kernel in the core library, the same structure the same file structure design exists in the runtime module. IFunction is the base class for all the functions, it has two child interfaces: ICLSimpleFunction and INESimpleFunction that are used as base class for functions which call a single kernel.
-The new operator has to implement %validate(), configure() and run(), these methods will call the respective function in the kernel considering that the multi-threading is used for the kernels which are parallelizable, by default std::thread::hardware_concurrency() threads are used. For NEON function can be used CPPScheduler::set_num_threads() to manually set the number of threads, whereas for OpenCL kernels all the kernels are enqueued on the queue associated with CLScheduler and the queue is then flushed.
+The new operator has to implement %validate(), configure() and run(), these methods will call the respective function in the kernel considering that the multi-threading is used for the kernels which are parallelizable, by default std::thread::hardware_concurrency() threads are used. For Neon function can be used CPPScheduler::set_num_threads() to manually set the number of threads, whereas for OpenCL kernels all the kernels are enqueued on the queue associated with CLScheduler and the queue is then flushed.
For the runtime functions, there is an extra method implemented: prepare(), this method prepares the function for the run, it does all the heavy operations that are done only once (reshape the weight, release the memory not necessary after the reshape, etc). The prepare method can be called standalone or in the first run, if not called before, after then the function will be marked as prepared.
The files we add are:
@@ -214,7 +214,7 @@ void CLAddReshapeLayer::run()
@endcode
-For NEON:
+For Neon:
@code{.cpp}
using namespace arm_compute;
diff --git a/docs/06_functions_list.dox b/docs/06_functions_list.dox
index 61712a29f5..96dce94a89 100644
--- a/docs/06_functions_list.dox
+++ b/docs/06_functions_list.dox
@@ -29,7 +29,7 @@ namespace arm_compute
@tableofcontents
-@section S6_1 NEON functions
+@section S6_1 Neon functions
- @ref IFunction
- @ref INESimpleFunction
diff --git a/docs/07_errata.dox b/docs/07_errata.dox
index 994b8c5bd7..7436f14bbc 100644
--- a/docs/07_errata.dox
+++ b/docs/07_errata.dox
@@ -42,7 +42,7 @@ namespace arm_compute
- Mali DDK r1p0 - r8p0, and
- Linux kernel >= 4.4
-- On Android with arm64-v8a/arm64-v8.2-a architecture, NEON validation tests can fail when compiled using Android Ndk
+- On Android with arm64-v8a/arm64-v8.2-a architecture, Neon validation tests can fail when compiled using Android Ndk
>= r18b in debug mode (https://github.com/android/ndk/issues/1135).
- Versions Affected: >= v19.11
- OSs Affected: Android
diff --git a/docs/ComputeLibrary.dir b/docs/ComputeLibrary.dir
index 7733e531cd..8b77ed4f02 100644
--- a/docs/ComputeLibrary.dir
+++ b/docs/ComputeLibrary.dir
@@ -64,15 +64,15 @@
*/
/** @dir src/core/NEON
- * @brief NEON backend core: kernels and utilities.
+ * @brief Neon backend core: kernels and utilities.
*/
/** @file src/core/NEON/NEKernels.h
- * @brief Includes all the NEON kernels at once
+ * @brief Includes all the Neon kernels at once
*/
/** @dir src/core/NEON/kernels
- * @brief Folder containing all the NEON kernels
+ * @brief Folder containing all the Neon kernels
*/
/** @dir arm_compute/core/utils
@@ -100,7 +100,7 @@
*/
/** @dir arm_compute/graph/backends/NEON
- * @brief NEON specific operations
+ * @brief Neon specific operations
*/
/** @dir arm_compute/graph/detail
@@ -160,7 +160,7 @@
*/
/** @file arm_compute/runtime/CPP/CPPScheduler.h
- * @brief Basic pool of threads to execute CPP/NEON code on several cores in parallel.
+ * @brief Basic pool of threads to execute CPP/Neon code on several cores in parallel.
*/
/** @dir arm_compute/runtime/CPP/functions
@@ -188,15 +188,15 @@
*/
/** @dir arm_compute/runtime/NEON
- * @brief NEON backend runtime interface.
+ * @brief Neon backend runtime interface.
*/
/** @file arm_compute/runtime/NEON/NEFunctions.h
- * @brief Includes all the NEON functions at once.
+ * @brief Includes all the Neon functions at once.
*/
/** @dir arm_compute/runtime/NEON/functions
- * @brief Folder containing all the NEON functions.
+ * @brief Folder containing all the Neon functions.
*/
/** @dir arm_compute/runtime/OMP
@@ -223,8 +223,8 @@
* -# cl_*.cpp --> OpenCL examples
* -# gc_*.cpp --> GLES compute shaders examples
* -# graph_*.cpp --> Graph examples
- * -# neoncl_*.cpp --> NEON / OpenCL interoperability examples
- * -# neon_*.cpp --> NEON examples
+ * -# neoncl_*.cpp --> Neon / OpenCL interoperability examples
+ * -# neon_*.cpp --> Neon examples
*/
/** @dir examples/gemm_tuner
@@ -252,11 +252,11 @@
*/
/** @dir src/core/NEON/wrapper
- * @brief NEON wrapper used to simplify code
+ * @brief Neon wrapper used to simplify code
*/
/** @file src/core/NEON/wrapper/traits.h
- * @brief Traits defined on NEON vectors
+ * @brief Traits defined on Neon vectors
*/
/** @file src/core/NEON/wrapper/wrapper.h
@@ -264,7 +264,7 @@
*/
/** @dir src/core/NEON/wrapper/intrinsics
- * @brief NEON intrinsics wrappers
+ * @brief Neon intrinsics wrappers
*/
/** @dir src/core/NEON/wrapper/scalar
@@ -300,7 +300,7 @@
*/
/** @dir tests/NEON
- * @brief NEON accessors.
+ * @brief Neon accessors.
*/
/** @dir tests/benchmark
@@ -316,7 +316,7 @@
*/
/** @dir tests/benchmark/NEON
- * @brief NEON benchmarking tests.
+ * @brief Neon benchmarking tests.
*/
/** @dir tests/benchmark_examples
@@ -352,7 +352,7 @@
*/
/** @dir tests/validation/NEON
- * @brief NEON validation tests.
+ * @brief Neon validation tests.
*/
/** @dir tests/validation/reference
diff --git a/examples/neon_cnn.cpp b/examples/neon_cnn.cpp
index 339c8c1a81..11bb0884bd 100644
--- a/examples/neon_cnn.cpp
+++ b/examples/neon_cnn.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -257,7 +257,7 @@ private:
Tensor out_fc0{};
Tensor out_softmax{};
- // NEON allocator
+ // Neon allocator
Allocator allocator{};
// Memory groups
diff --git a/examples/neon_copy_objects.cpp b/examples/neon_copy_objects.cpp
index 2fbc128cdd..824e419cf7 100644
--- a/examples/neon_copy_objects.cpp
+++ b/examples/neon_copy_objects.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -140,7 +140,7 @@ public:
}
void do_run() override
{
- // Run NEON softmax:
+ // Run Neon softmax:
softmax.run();
}
void do_teardown() override
diff --git a/examples/neoncl_scale_median_gaussian.cpp b/examples/neoncl_scale_median_gaussian.cpp
index 948aff23bb..2580a35f24 100644
--- a/examples/neoncl_scale_median_gaussian.cpp
+++ b/examples/neoncl_scale_median_gaussian.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -36,7 +36,7 @@
using namespace arm_compute;
using namespace utils;
-/** Example demonstrating how to use both CL and NEON functions in the same pipeline
+/** Example demonstrating how to use both CL and Neon functions in the same pipeline
*
* @param[in] argc Number of arguments
* @param[in] argv Arguments ( [optional] Path to PPM image to process )
@@ -46,7 +46,7 @@ class NEONCLScaleMedianGaussianExample : public Example
public:
bool do_setup(int argc, char **argv) override
{
- /** [NEON / OpenCL Interop] */
+ /** [Neon / OpenCL Interop] */
PPMLoader ppm;
CLScheduler::get().default_init();
@@ -88,7 +88,7 @@ public:
ppm.fill_image(src);
const std::string output_filename = std::string(argv[1]) + "_out.ppm";
}
- /** [NEON / OpenCL Interop] */
+ /** [Neon / OpenCL Interop] */
return true;
}
@@ -97,11 +97,11 @@ public:
// Enqueue and flush the OpenCL kernel:
scale.run();
- // Do a blocking map of the input and output buffers of the NEON function:
+ // Do a blocking map of the input and output buffers of the Neon function:
scale_median.map();
median_gauss.map();
- // Run the NEON function:
+ // Run the Neon function:
median.run();
// Unmap the output buffer before it's used again by OpenCL:
diff --git a/scripts/include_functions_kernels.py b/scripts/include_functions_kernels.py
index 4db47ea754..19f140ea3b 100755..100644
--- a/scripts/include_functions_kernels.py
+++ b/scripts/include_functions_kernels.py
@@ -9,7 +9,7 @@ src_path ="src"
Target = collections.namedtuple('Target', 'name prefix basepath')
core_targets = [
- Target("NEON", "NE", src_path), # NEON kernels are under src
+ Target("NEON", "NE", src_path), # Neon kernels are under src
Target("CL", "CL", src_path), # CL kernels are under src
Target("CPP", "CPP", armcv_path), # CPP kernels are under arm_compute
Target("GLES_COMPUTE", "GC", armcv_path) # GLES kernels are under arm_compute
diff --git a/src/core/CL/cl_kernels/helpers_asymm.h b/src/core/CL/cl_kernels/helpers_asymm.h
index 59c8fa606d..eea4458170 100644
--- a/src/core/CL/cl_kernels/helpers_asymm.h
+++ b/src/core/CL/cl_kernels/helpers_asymm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -192,7 +192,7 @@ inline float dequantize_qasymm8_signed(char input, float offset, float scale)
/** Each bit of the result is set to the corresponding bit of either then_val or
* else_val depending on whether the corresponding bit of if_mask is set.
- * Equivalent to the VBSL instruction in ARM NEON.
+ * Equivalent to the VBSL instruction in Arm Neon.
*
* @param[in] size Size of vector.
*
@@ -320,7 +320,7 @@ inline float dequantize_qasymm8_signed(char input, float offset, float scale)
}
/** Calculates (a+b)/2, rounded to the nearest integer.
- * Equivalent to VRHADD in the ARM NEON instruction set.
+ * Equivalent to VRHADD in the Arm Neon instruction set.
*
* @param[in] size Size of vector.
*
diff --git a/src/core/NEON/INEKernel.h b/src/core/NEON/INEKernel.h
index 7ad20166d8..dde8310ecf 100644
--- a/src/core/NEON/INEKernel.h
+++ b/src/core/NEON/INEKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@
namespace arm_compute
{
-/** Common interface for all kernels implemented in NEON. */
+/** Common interface for all kernels implemented in Neon. */
using INEKernel = ICPPKernel;
} // namespace arm_compute
#endif /*ARM_COMPUTE_INEKERNEL_H */
diff --git a/src/core/NEON/INESimpleKernel.h b/src/core/NEON/INESimpleKernel.h
index da32d6619e..d2b6de427b 100644
--- a/src/core/NEON/INESimpleKernel.h
+++ b/src/core/NEON/INESimpleKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@
namespace arm_compute
{
-/** Interface for simple NEON kernels having 1 tensor input and 1 tensor output */
+/** Interface for simple Neon kernels having 1 tensor input and 1 tensor output */
using INESimpleKernel = ICPPSimpleKernel;
} // namespace arm_compute
#endif /*ARM_COMPUTE_INESIMPLEKERNEL_H */
diff --git a/src/core/NEON/NEKernels.h b/src/core/NEON/NEKernels.h
index 66309f9296..b962c9eeee 100644
--- a/src/core/NEON/NEKernels.h
+++ b/src/core/NEON/NEKernels.h
@@ -24,7 +24,7 @@
#ifndef ARM_COMPUTE_NEKERNELS_H
#define ARM_COMPUTE_NEKERNELS_H
-/* Header regrouping all the NEON kernels */
+/* Header regrouping all the Neon kernels */
#include "src/core/NEON/kernels/NEAbsoluteDifferenceKernel.h"
#include "src/core/NEON/kernels/NEAccumulateKernel.h"
#include "src/core/NEON/kernels/NEBatchNormalizationLayerKernel.h"
diff --git a/src/core/NEON/kernels/NEBatchNormalizationLayerKernel.cpp b/src/core/NEON/kernels/NEBatchNormalizationLayerKernel.cpp
index 6f2c72a970..7f707d7f1a 100644
--- a/src/core/NEON/kernels/NEBatchNormalizationLayerKernel.cpp
+++ b/src/core/NEON/kernels/NEBatchNormalizationLayerKernel.cpp
@@ -148,7 +148,7 @@ validate_arguments(const ITensorInfo *input, const ITensorInfo *output, const IT
template <typename T, bool fused_activation, typename F>
void NEBatchNormalizationLayerKernel::batch_normalization_nchw(const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<T, wrapper::traits::BitWidth::W128>;
const int window_step_x = 16 / sizeof(T);
@@ -164,7 +164,7 @@ void NEBatchNormalizationLayerKernel::batch_normalization_nchw(const Window &win
F activation_functor(_act_info);
// Hold information about the current feature map we are iterating.
- // Only compute denominator and NEON vectors once per feature map.
+ // Only compute denominator and Neon vectors once per feature map.
int slice = -1;
const auto input_mean = reinterpret_cast<const T *>(_mean->ptr_to_element(Coordinates(0, 0)));
diff --git a/src/core/NEON/kernels/NEBox3x3Kernel.h b/src/core/NEON/kernels/NEBox3x3Kernel.h
index f6a64a7bb4..4f9ac18219 100644
--- a/src/core/NEON/kernels/NEBox3x3Kernel.h
+++ b/src/core/NEON/kernels/NEBox3x3Kernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform a Box 3x3 filter */
+/** Neon kernel to perform a Box 3x3 filter */
class NEBox3x3Kernel : public INESimpleKernel
{
public:
@@ -63,7 +63,7 @@ public:
};
#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
-/** NEON kernel to perform a Box 3x3 filter for FP16 datatype
+/** Neon kernel to perform a Box 3x3 filter for FP16 datatype
*/
class NEBox3x3FP16Kernel : public NEBox3x3Kernel
{
@@ -88,7 +88,7 @@ public:
void run(const Window &window, const ThreadInfo &info) override;
};
#else /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
-/** NEON kernel to perform a Box 3x3 filter for FP16 datatype */
+/** Neon kernel to perform a Box 3x3 filter for FP16 datatype */
using NEBox3x3FP16Kernel = NEBox3x3Kernel;
#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
} // namespace arm_compute
diff --git a/src/core/NEON/kernels/NECannyEdgeKernel.h b/src/core/NEON/kernels/NECannyEdgeKernel.h
index eff735259d..f1d24410f7 100644
--- a/src/core/NEON/kernels/NECannyEdgeKernel.h
+++ b/src/core/NEON/kernels/NECannyEdgeKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -85,7 +85,7 @@ protected:
ITensor *_phase; /**< Destination tensor - Quantized phase */
};
-/** NEON kernel to perform Non-Maxima suppression for Canny Edge.
+/** Neon kernel to perform Non-Maxima suppression for Canny Edge.
*
* @note This kernel is meant to be used alongside CannyEdge and performs a non-maxima suppression using magnitude and phase of input
* to characterize points as possible edges. Thus, at the end, each point will be set to EDGE, NO_EDGE or MAYBE.
@@ -148,7 +148,7 @@ private:
int32_t _upper_thr; /**< Upper threshold used for the hysteresis */
};
-/** NEON kernel to perform Edge tracing */
+/** Neon kernel to perform Edge tracing */
class NEEdgeTraceKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEChannelShuffleLayerKernel.cpp b/src/core/NEON/kernels/NEChannelShuffleLayerKernel.cpp
index 6e16f24956..4a2213a30b 100644
--- a/src/core/NEON/kernels/NEChannelShuffleLayerKernel.cpp
+++ b/src/core/NEON/kernels/NEChannelShuffleLayerKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,7 @@ namespace
{
Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output, unsigned int num_groups)
{
- // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON_DATA_LAYOUT_NOT_IN(input, DataLayout::NCHW, DataLayout::NHWC);
diff --git a/src/core/NEON/kernels/NECol2ImKernel.cpp b/src/core/NEON/kernels/NECol2ImKernel.cpp
index 97b68d1321..bbc86a9a05 100644
--- a/src/core/NEON/kernels/NECol2ImKernel.cpp
+++ b/src/core/NEON/kernels/NECol2ImKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -44,7 +44,7 @@ namespace
{
Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output, const Size2D &convolved_dims)
{
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
// Validate configured output
diff --git a/src/core/NEON/kernels/NECol2ImKernel.h b/src/core/NEON/kernels/NECol2ImKernel.h
index 59d1d741b6..00a519d229 100644
--- a/src/core/NEON/kernels/NECol2ImKernel.h
+++ b/src/core/NEON/kernels/NECol2ImKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform col2im reshaping.
+/** Neon kernel to perform col2im reshaping.
*
* Rearranges each matrix column into image blocks. It's the inverse operation of @ref NEIm2ColKernel.
*
diff --git a/src/core/NEON/kernels/NEConvertFullyConnectedWeightsKernel.cpp b/src/core/NEON/kernels/NEConvertFullyConnectedWeightsKernel.cpp
index 597c283a9c..101d1384d0 100644
--- a/src/core/NEON/kernels/NEConvertFullyConnectedWeightsKernel.cpp
+++ b/src/core/NEON/kernels/NEConvertFullyConnectedWeightsKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -69,7 +69,7 @@ Status NEConvertFullyConnectedWeightsKernel::validate(const ITensorInfo *input,
DataLayout data_layout)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON(input->num_dimensions() != 2);
ARM_COMPUTE_RETURN_ERROR_ON(input->dimension(1) != original_input_shape.total_size_lower(3));
diff --git a/src/core/NEON/kernels/NEConvertQuantizedSignednessKernel.h b/src/core/NEON/kernels/NEConvertQuantizedSignednessKernel.h
index 39e5300238..0be1fbe5aa 100644
--- a/src/core/NEON/kernels/NEConvertQuantizedSignednessKernel.h
+++ b/src/core/NEON/kernels/NEConvertQuantizedSignednessKernel.h
@@ -32,7 +32,7 @@ namespace arm_compute
// Forward declarations
class ITensor;
-/** NEON kernel to convert asymmetric signed to asymmetric signed and vice-versa */
+/** Neon kernel to convert asymmetric signed to asymmetric signed and vice-versa */
class NEConvertQuantizedSignednessKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEConvolutionKernel.cpp b/src/core/NEON/kernels/NEConvolutionKernel.cpp
index bac27430f9..075de41203 100644
--- a/src/core/NEON/kernels/NEConvolutionKernel.cpp
+++ b/src/core/NEON/kernels/NEConvolutionKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -374,7 +374,7 @@ void NEConvolutionKernel<3>::convolution(const Window &win)
Iterator input(_input, win);
Iterator output(_output, win);
- // Load the matrix's coefficients into NEON registers:
+ // Load the matrix's coefficients into Neon registers:
const int16x4_t mat00 = vld1_dup_s16(_convolution.data());
const int16x4_t mat01 = vld1_dup_s16(_convolution.data() + 1);
const int16x4_t mat02 = vld1_dup_s16(_convolution.data() + 2);
diff --git a/src/core/NEON/kernels/NEDerivativeKernel.cpp b/src/core/NEON/kernels/NEDerivativeKernel.cpp
index 8d641a33b9..e5780ea264 100644
--- a/src/core/NEON/kernels/NEDerivativeKernel.cpp
+++ b/src/core/NEON/kernels/NEDerivativeKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -83,11 +83,11 @@ void NEDerivativeKernel::configure(const ITensor *input, ITensor *output_x, ITen
AccessWindowHorizontal out_x_access(output_x == nullptr ? nullptr : output_x->info(), 0, num_elems_processed_per_iteration);
AccessWindowHorizontal out_y_access(output_y == nullptr ? nullptr : output_y->info(), 0, num_elems_processed_per_iteration);
- // TODO(COMPMID-1503) Fix x-access input bug in NEON kernel instead of '+2'
+ // TODO(COMPMID-1503) Fix x-access input bug in Neon kernel instead of '+2'
AccessWindowHorizontal in_x_access(input->info(), -border_size().left, num_elems_processed_per_iteration + 2);
AccessWindowRectangle in_y_access(input->info(), 0, -border_size().left, num_elems_processed_per_iteration, num_rows_read_per_iteration);
- // TODO(COMPMID-1503) Fix x-access input bug in NEON kernel instead of '+2'
+ // TODO(COMPMID-1503) Fix x-access input bug in Neon kernel instead of '+2'
AccessWindowRectangle in_xy_access(input->info(), -border_size().left, -border_size().top, num_elems_processed_per_iteration + 2, num_rows_read_per_iteration);
if(run_der_x && run_der_y)
diff --git a/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp b/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp
index 87b9fb1bf1..77742163fa 100644
--- a/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp
+++ b/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -149,7 +149,7 @@ inline bool run_optim_small_tensor(const ITensor *t)
// Optimized convolver for 1x1 kernels used only where input width and height are both <= 8
// For big Z as in Input=7x7x832, this implementation is faster than the general code becuase it doesn't need to
-// store intermidiate results in memory. Temporary results are stored in NEON registers directly and then written to the output buffer.
+// store intermidiate results in memory. Temporary results are stored in Neon registers directly and then written to the output buffer.
template <unsigned int stridex>
class convolver_w1x1_i8x8_f32
{
@@ -1381,4 +1381,4 @@ void NEDirectConvolutionLayerKernel::run(const Window &window, const ThreadInfo
}
}
}
-} // namespace arm_compute \ No newline at end of file
+} // namespace arm_compute
diff --git a/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h b/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h
index 94c97cf521..58d385a138 100644
--- a/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h
+++ b/src/core/NEON/kernels/NEDirectConvolutionLayerKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON interface for Direct Convolution Layer kernel */
+/** Neon interface for Direct Convolution Layer kernel */
class NEDirectConvolutionLayerKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.cpp b/src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.cpp
index de5a88e812..f072851240 100644
--- a/src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.cpp
+++ b/src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@ typename std::enable_if<arm_compute::utils::traits::is_floating_point<T>::value,
output_stage_nchw(ITensor *input, const ITensor *bias, const Window &window, ITensor *output,
int result_fixedpoint_multiplier, int result_shift, int result_offset_after_shift, bool has_bias)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<T, wrapper::traits::BitWidth::W128>;
ARM_COMPUTE_ERROR_ON(input->info()->data_layout() == DataLayout::UNKNOWN);
diff --git a/src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h b/src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h
index b1b88103bf..cd0710d0c1 100644
--- a/src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h
+++ b/src/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@
namespace arm_compute
{
class ITensor;
-/** NEON kernel to accumulate the biases, if provided, or downscale in case of quantized input.
+/** Neon kernel to accumulate the biases, if provided, or downscale in case of quantized input.
*
* @note We assume bias to be shared
* @note For quantized computations (i.e. @p input of S32 type) the output data type for auto-initialization must be passed as part
diff --git a/src/core/NEON/kernels/NEFastCornersKernel.h b/src/core/NEON/kernels/NEFastCornersKernel.h
index a4086afb0c..f981d72a03 100644
--- a/src/core/NEON/kernels/NEFastCornersKernel.h
+++ b/src/core/NEON/kernels/NEFastCornersKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -34,7 +34,7 @@ namespace arm_compute
class ITensor;
using IImage = ITensor;
-/** NEON kernel to perform fast corners */
+/** Neon kernel to perform fast corners */
class NEFastCornersKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEFillBorderKernel.cpp b/src/core/NEON/kernels/NEFillBorderKernel.cpp
index 10384d4176..70178dffc0 100644
--- a/src/core/NEON/kernels/NEFillBorderKernel.cpp
+++ b/src/core/NEON/kernels/NEFillBorderKernel.cpp
@@ -103,7 +103,7 @@ void NEFillBorderKernel::configure(ITensor *tensor, BorderSize border_size, Bord
void NEFillBorderKernel::configure(ITensorInfo *tensor, BorderSize border_size, BorderMode border_mode, const PixelValue &constant_border_value)
{
ARM_COMPUTE_ERROR_ON_NULLPTR(tensor);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_ERROR_ON(tensor->data_type() == DataType::UNKNOWN);
_border_size = border_size;
diff --git a/src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.cpp b/src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.cpp
index 5d178ea85b..6b2383f043 100644
--- a/src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.cpp
+++ b/src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -47,7 +47,7 @@ namespace
Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(input, output);
diff --git a/src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.h b/src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.h
index 85939ebae9..92fbd12a54 100644
--- a/src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.h
+++ b/src/core/NEON/kernels/NEGEMMInterleave4x4Kernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to interleave the elements of a matrix
+/** Neon kernel to interleave the elements of a matrix
*
* This function puts the values in a 4x4 block of Matrix A on the same row (Interleaved values)
*
diff --git a/src/core/NEON/kernels/NEGEMMLowpMatrixMultiplyKernel.h b/src/core/NEON/kernels/NEGEMMLowpMatrixMultiplyKernel.h
index 14d03fe3eb..dfdb7b3236 100644
--- a/src/core/NEON/kernels/NEGEMMLowpMatrixMultiplyKernel.h
+++ b/src/core/NEON/kernels/NEGEMMLowpMatrixMultiplyKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to multiply matrices
+/** Neon kernel to multiply matrices
*
* @note @ref NEGEMMLowpMatrixMultiplyKernel low precision matrix product kernel
* This kernel performs the following computation:
diff --git a/src/core/NEON/kernels/NEGEMMLowpOffsetContributionKernel.h b/src/core/NEON/kernels/NEGEMMLowpOffsetContributionKernel.h
index 0f37e584b9..9911ffc0f4 100644
--- a/src/core/NEON/kernels/NEGEMMLowpOffsetContributionKernel.h
+++ b/src/core/NEON/kernels/NEGEMMLowpOffsetContributionKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel used to add the offset contribution after @ref NEGEMMLowpMatrixMultiplyKernel. The computation is performed in-place
+/** Neon kernel used to add the offset contribution after @ref NEGEMMLowpMatrixMultiplyKernel. The computation is performed in-place
*
* This kernel takes a final int32 accumulator value (the output of @ref NEGEMMLowpMatrixMultiplyKernel),
* and adds to it the offset contribution of matrix A and matrix B in-place.
diff --git a/src/core/NEON/kernels/NEGEMMLowpOffsetContributionOutputStageKernel.h b/src/core/NEON/kernels/NEGEMMLowpOffsetContributionOutputStageKernel.h
index 4c68fb0943..39fbd8eb0e 100644
--- a/src/core/NEON/kernels/NEGEMMLowpOffsetContributionOutputStageKernel.h
+++ b/src/core/NEON/kernels/NEGEMMLowpOffsetContributionOutputStageKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel used to add the offset contribution and perform the output stage after @ref NEGEMMLowpMatrixMultiplyKernel.
+/** Neon kernel used to add the offset contribution and perform the output stage after @ref NEGEMMLowpMatrixMultiplyKernel.
*
* The computation is performed in-place
*
diff --git a/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ScaleKernel.h b/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ScaleKernel.h
index 42ef570f77..63d80aaf1b 100644
--- a/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ScaleKernel.h
+++ b/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ScaleKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel used to quantize down the int32 accumulator values of GEMMLowp to QASYMM8/QASYMM8_SIGNED
+/** Neon kernel used to quantize down the int32 accumulator values of GEMMLowp to QASYMM8/QASYMM8_SIGNED
*
* This kernel takes a final int32 accumulator value (the output of @ref NEGEMMLowpMatrixMultiplyKernel), and processes it to obtain the final QASYMM8/QASYMM8_SIGNED value.
* The following computations will be performed by the kernel:
diff --git a/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel.h b/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel.h
index d04e713cb8..8e92ba6eca 100644
--- a/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel.h
+++ b/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel used to quantize down the int32 accumulator values of GEMMLowp to QSYMM16
+/** Neon kernel used to quantize down the int32 accumulator values of GEMMLowp to QSYMM16
*
* This kernel takes a final int32 accumulator value (the output of @ref NEGEMMLowpMatrixMultiplyKernel), and processes it to obtain the final QSYMM16 value.
* The following computations will be performed by the kernel:
diff --git a/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel.h b/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel.h
index 55c07fbb5a..9b51a3ba84 100644
--- a/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel.h
+++ b/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel used to quantize down the int32 accumulator values of GEMMLowp to QASYMM8_SIGNED
+/** Neon kernel used to quantize down the int32 accumulator values of GEMMLowp to QASYMM8_SIGNED
*
* This kernel takes a final int32 accumulator value (the output of @ref NEGEMMLowpMatrixMultiplyKernel), and processes it to obtain the final QASYMM8_SIGNED value.
* The following computations will be performed by the kernel:
diff --git a/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel.h b/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel.h
index 1a8de1c441..4d43afaab2 100644
--- a/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel.h
+++ b/src/core/NEON/kernels/NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel used to quantize down the int32 accumulator values of GEMMLowp to QASYMM8
+/** Neon kernel used to quantize down the int32 accumulator values of GEMMLowp to QASYMM8
*
* This kernel takes a final int32 accumulator value (the output of @ref NEGEMMLowpMatrixMultiplyKernel), and processes it to obtain the final QASYMM8 value.
* The following computations will be performed by the kernel:
diff --git a/src/core/NEON/kernels/NEGEMMLowpReductionKernel.h b/src/core/NEON/kernels/NEGEMMLowpReductionKernel.h
index 655658cb6c..521adbfca4 100644
--- a/src/core/NEON/kernels/NEGEMMLowpReductionKernel.h
+++ b/src/core/NEON/kernels/NEGEMMLowpReductionKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@ namespace arm_compute
class ITensor;
struct GEMMLowpReductionKernelInfo;
-/** Common interface for all NEON reduction kernels */
+/** Common interface for all Neon reduction kernels */
class INEGEMMLowpReductionKernel : public INEKernel
{
public:
@@ -69,7 +69,7 @@ protected:
bool _mul_by_scalar;
};
-/** NEON kernel used to compute the row-vectors of sums of all the entries in each row of Matrix A.
+/** Neon kernel used to compute the row-vectors of sums of all the entries in each row of Matrix A.
*
* @note This stage is needed to handle the offset of matrix product
* https://github.com/google/gemmlowp/blob/master/doc/low-precision.md
@@ -130,7 +130,7 @@ private:
void run_internal(const Window &window);
};
-/** NEON kernel used to compute the row-vectors of sums of all the entries in each column of Matrix B.
+/** Neon kernel used to compute the row-vectors of sums of all the entries in each column of Matrix B.
*
* @note This stage is needed to handle the offset of matrix product
* https://github.com/google/gemmlowp/blob/master/doc/low-precision.md
diff --git a/src/core/NEON/kernels/NEGEMMMatrixAdditionKernel.h b/src/core/NEON/kernels/NEGEMMMatrixAdditionKernel.h
index 48377838d2..f9ff143e07 100644
--- a/src/core/NEON/kernels/NEGEMMMatrixAdditionKernel.h
+++ b/src/core/NEON/kernels/NEGEMMMatrixAdditionKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform the in-place matrix addition between 2 matrices taking into account that the second matrix might be weighted by a scalar value beta:
+/** Neon kernel to perform the in-place matrix addition between 2 matrices taking into account that the second matrix might be weighted by a scalar value beta:
*
* @note [ MTX_OUT = MTX_0 + beta * MTX_1 ] with MTX_0 and MTX_1 of the same size
*
diff --git a/src/core/NEON/kernels/NEGEMMMatrixMultiplyKernel.h b/src/core/NEON/kernels/NEGEMMMatrixMultiplyKernel.h
index 1ea948de63..e2945ee117 100644
--- a/src/core/NEON/kernels/NEGEMMMatrixMultiplyKernel.h
+++ b/src/core/NEON/kernels/NEGEMMMatrixMultiplyKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to multiply two input matrices "A" and "B". All elements of the output matrix/vector will be multiplied by alpha after the matrix multiplication
+/** Neon kernel to multiply two input matrices "A" and "B". All elements of the output matrix/vector will be multiplied by alpha after the matrix multiplication
*
* @note If the output tensor is a matrix, the implementation assumes that the input tensors @p input0 and @p input1 are both matrices and reshaped respectively with @ref NEGEMMInterleave4x4Kernel" and @ref NEGEMMTranspose1xWKernel
* @note If the output tensor is a vector and the data type is F32, the implementation assumes that the first input tensor @p input0 is a vector and the second input tensor @p input1 a matrix. The implementation also assumes that both tensors have not been reshaped
diff --git a/src/core/NEON/kernels/NEGEMMTranspose1xWKernel.cpp b/src/core/NEON/kernels/NEGEMMTranspose1xWKernel.cpp
index 6d9f921b02..cea95749f8 100644
--- a/src/core/NEON/kernels/NEGEMMTranspose1xWKernel.cpp
+++ b/src/core/NEON/kernels/NEGEMMTranspose1xWKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -51,7 +51,7 @@ Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input);
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
if(output->total_size() != 0)
{
diff --git a/src/core/NEON/kernels/NEGEMMTranspose1xWKernel.h b/src/core/NEON/kernels/NEGEMMTranspose1xWKernel.h
index 7120943a90..583588a1c1 100644
--- a/src/core/NEON/kernels/NEGEMMTranspose1xWKernel.h
+++ b/src/core/NEON/kernels/NEGEMMTranspose1xWKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -31,7 +31,7 @@ namespace arm_compute
// Forward declarations
class ITensor;
-/** NEON kernel which transposes the elements of a matrix in chunks of 1xW, where W is equal to (16 / element size of the tensor)
+/** Neon kernel which transposes the elements of a matrix in chunks of 1xW, where W is equal to (16 / element size of the tensor)
*
* Following an example of how the transposition1xW works when the input data is F32
*
diff --git a/src/core/NEON/kernels/NEGatherKernel.h b/src/core/NEON/kernels/NEGatherKernel.h
index d81e34c39c..46b41b28e3 100644
--- a/src/core/NEON/kernels/NEGatherKernel.h
+++ b/src/core/NEON/kernels/NEGatherKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
// Forward declarations
class ITensor;
-/** Kernel to perform other operation on NEON */
+/** Kernel to perform other operation on Neon */
class NEGatherKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEGaussian3x3Kernel.h b/src/core/NEON/kernels/NEGaussian3x3Kernel.h
index 8973b48e7a..7ceea2e7c1 100644
--- a/src/core/NEON/kernels/NEGaussian3x3Kernel.h
+++ b/src/core/NEON/kernels/NEGaussian3x3Kernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform a Gaussian 3x3 filter */
+/** Neon kernel to perform a Gaussian 3x3 filter */
class NEGaussian3x3Kernel : public INESimpleKernel
{
public:
diff --git a/src/core/NEON/kernels/NEGaussian5x5Kernel.h b/src/core/NEON/kernels/NEGaussian5x5Kernel.h
index f4bca55637..2c7262f827 100644
--- a/src/core/NEON/kernels/NEGaussian5x5Kernel.h
+++ b/src/core/NEON/kernels/NEGaussian5x5Kernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform a Gaussian 5x5 filter (horizontal pass) */
+/** Neon kernel to perform a Gaussian 5x5 filter (horizontal pass) */
class NEGaussian5x5HorKernel : public INESimpleKernel
{
public:
@@ -67,7 +67,7 @@ private:
BorderSize _border_size;
};
-/** NEON kernel to perform a Gaussian 5x5 filter (vertical pass) */
+/** Neon kernel to perform a Gaussian 5x5 filter (vertical pass) */
class NEGaussian5x5VertKernel : public INESimpleKernel
{
public:
diff --git a/src/core/NEON/kernels/NEGaussianPyramidKernel.h b/src/core/NEON/kernels/NEGaussianPyramidKernel.h
index e852db2699..d943990535 100644
--- a/src/core/NEON/kernels/NEGaussianPyramidKernel.h
+++ b/src/core/NEON/kernels/NEGaussianPyramidKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform a GaussianPyramid (horizontal pass) */
+/** Neon kernel to perform a GaussianPyramid (horizontal pass) */
class NEGaussianPyramidHorKernel : public INESimpleKernel
{
public:
@@ -66,7 +66,7 @@ private:
int _l2_load_offset;
};
-/** NEON kernel to perform a GaussianPyramid (vertical pass) */
+/** Neon kernel to perform a GaussianPyramid (vertical pass) */
class NEGaussianPyramidVertKernel : public INESimpleKernel
{
public:
diff --git a/src/core/NEON/kernels/NEHOGDescriptorKernel.h b/src/core/NEON/kernels/NEHOGDescriptorKernel.h
index 7845bc2cdf..e9cd47b099 100644
--- a/src/core/NEON/kernels/NEHOGDescriptorKernel.h
+++ b/src/core/NEON/kernels/NEHOGDescriptorKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform HOG Orientation Binning */
+/** Neon kernel to perform HOG Orientation Binning */
class NEHOGOrientationBinningKernel : public INEKernel
{
public:
@@ -91,7 +91,7 @@ private:
float _phase_scale;
};
-/** NEON kernel to perform HOG block normalization */
+/** Neon kernel to perform HOG block normalization */
class NEHOGBlockNormalizationKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEHOGDetectorKernel.h b/src/core/NEON/kernels/NEHOGDetectorKernel.h
index 45c28099c8..e4c699fbfb 100644
--- a/src/core/NEON/kernels/NEHOGDetectorKernel.h
+++ b/src/core/NEON/kernels/NEHOGDetectorKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -33,7 +33,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform HOG detector kernel using linear SVM */
+/** Neon kernel to perform HOG detector kernel using linear SVM */
class NEHOGDetectorKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEHarrisCornersKernel.h b/src/core/NEON/kernels/NEHarrisCornersKernel.h
index 4b794107a2..85f80878cc 100644
--- a/src/core/NEON/kernels/NEHarrisCornersKernel.h
+++ b/src/core/NEON/kernels/NEHarrisCornersKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -76,7 +76,7 @@ protected:
BorderSize _border_size; /**< Border size */
};
-/** Template NEON kernel to perform Harris Score.
+/** Template Neon kernel to perform Harris Score.
* The implementation supports 3, 5, and 7 for the block_size
*/
template <int32_t block_size>
diff --git a/src/core/NEON/kernels/NEIm2ColKernel.cpp b/src/core/NEON/kernels/NEIm2ColKernel.cpp
index 72821c890d..728cecd074 100644
--- a/src/core/NEON/kernels/NEIm2ColKernel.cpp
+++ b/src/core/NEON/kernels/NEIm2ColKernel.cpp
@@ -55,7 +55,7 @@ Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output, c
ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::BFLOAT16, DataType::F16, DataType::F32);
ARM_COMPUTE_RETURN_ERROR_ON(is_data_type_quantized(input->data_type()) && has_bias);
ARM_COMPUTE_RETURN_ERROR_ON((dilation.x() < 1) || (dilation.y() < 1));
- ARM_COMPUTE_RETURN_ERROR_ON_MSG(num_groups > 1, "Number of groups greater than one are not supported on NEON");
+ ARM_COMPUTE_RETURN_ERROR_ON_MSG(num_groups > 1, "Number of groups greater than one are not supported on Neon");
// Since there's no implicit padding added, check the total input spatial dimensions (with conv paddings) are big enough for the kernel dimensions
const unsigned int width_idx = get_data_layout_dimension_index(input->data_layout(), DataLayoutDimension::WIDTH);
diff --git a/src/core/NEON/kernels/NEInstanceNormalizationLayerKernel.cpp b/src/core/NEON/kernels/NEInstanceNormalizationLayerKernel.cpp
index 08bf6f0e76..a3f7d8d634 100644
--- a/src/core/NEON/kernels/NEInstanceNormalizationLayerKernel.cpp
+++ b/src/core/NEON/kernels/NEInstanceNormalizationLayerKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -82,7 +82,7 @@ inline float16x8_t vector_float_norm(const float16x8_t &inputs, const float32x4_
template <typename T, typename AccType = T>
void instance_normalization_nchw(ITensor *input, ITensor *output, float gamma, float beta, float epsilon, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<T, wrapper::traits::BitWidth::W128>;
// Clear X/Y dimensions on execution window as we handle the planes manually
diff --git a/src/core/NEON/kernels/NELKTrackerKernel.h b/src/core/NEON/kernels/NELKTrackerKernel.h
index c24166c042..bc4f6ce296 100644
--- a/src/core/NEON/kernels/NELKTrackerKernel.h
+++ b/src/core/NEON/kernels/NELKTrackerKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -37,7 +37,7 @@ namespace arm_compute
{
class ITensor;
-/** Interface for NEON Array of Internal Key Points. */
+/** Interface for Neon Array of Internal Key Points. */
using INELKInternalKeypointArray = IArray<NELKInternalKeypoint>;
/** Interface for the Lucas-Kanade tracker kernel */
diff --git a/src/core/NEON/kernels/NENonMaximaSuppression3x3Kernel.h b/src/core/NEON/kernels/NENonMaximaSuppression3x3Kernel.h
index d32dfecfeb..7b0bc0c720 100644
--- a/src/core/NEON/kernels/NENonMaximaSuppression3x3Kernel.h
+++ b/src/core/NEON/kernels/NENonMaximaSuppression3x3Kernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@ namespace arm_compute
{
class ITensor;
-/** Interface to perform Non-Maxima suppression over a 3x3 window using NEON
+/** Interface to perform Non-Maxima suppression over a 3x3 window using Neon
*
* @note Used by @ref NEFastCorners and @ref NEHarrisCorners
*/
@@ -83,7 +83,7 @@ protected:
};
#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
-/** NEON kernel to perform Non-Maxima suppression 3x3 with intermediate results in FP16 if the input data type is FP32
+/** Neon kernel to perform Non-Maxima suppression 3x3 with intermediate results in FP16 if the input data type is FP32
*/
class NENonMaximaSuppression3x3FP16Kernel : public NENonMaximaSuppression3x3Kernel
{
@@ -101,7 +101,7 @@ public:
void configure(const ITensor *input, ITensor *output, bool border_undefined);
};
#else /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
-/** NEON kernel to perform Non-Maxima suppression 3x3 with intermediate results in FP16 if the input data type is FP32 */
+/** Neon kernel to perform Non-Maxima suppression 3x3 with intermediate results in FP16 if the input data type is FP32 */
using NENonMaximaSuppression3x3FP16Kernel = NENonMaximaSuppression3x3Kernel;
#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
} // namespace arm_compute
diff --git a/src/core/NEON/kernels/NENormalizationLayerKernel.cpp b/src/core/NEON/kernels/NENormalizationLayerKernel.cpp
index 27464d5b42..a7900ee074 100644
--- a/src/core/NEON/kernels/NENormalizationLayerKernel.cpp
+++ b/src/core/NEON/kernels/NENormalizationLayerKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -173,7 +173,7 @@ void NENormalizationLayerKernel::configure(const ITensor *input, const ITensor *
template <typename T, unsigned int S, unsigned int dim, bool do_2D_norm>
void NENormalizationLayerKernel::normalize_float(const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
Window win(window);
@@ -295,4 +295,4 @@ void NENormalizationLayerKernel::run(const Window &window, const ThreadInfo &inf
// Run function
(this->*_func)(window);
}
-} // namespace arm_compute \ No newline at end of file
+} // namespace arm_compute
diff --git a/src/core/NEON/kernels/NEPadLayerKernel.h b/src/core/NEON/kernels/NEPadLayerKernel.h
index ec4bdffdcd..af0dbfdc64 100644
--- a/src/core/NEON/kernels/NEPadLayerKernel.h
+++ b/src/core/NEON/kernels/NEPadLayerKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to add padding to a tensor
+/** Neon kernel to add padding to a tensor
*
* Add padding given padding information
*/
diff --git a/src/core/NEON/kernels/NEQLSTMLayerNormalizationKernel.h b/src/core/NEON/kernels/NEQLSTMLayerNormalizationKernel.h
index ba68171a59..5522ae889a 100644
--- a/src/core/NEON/kernels/NEQLSTMLayerNormalizationKernel.h
+++ b/src/core/NEON/kernels/NEQLSTMLayerNormalizationKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -31,7 +31,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform layer normalization */
+/** Neon kernel to perform layer normalization */
class NEQLSTMLayerNormalizationKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NERangeKernel.cpp b/src/core/NEON/kernels/NERangeKernel.cpp
index 8d11122ab2..f62c868dff 100644
--- a/src/core/NEON/kernels/NERangeKernel.cpp
+++ b/src/core/NEON/kernels/NERangeKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -43,7 +43,7 @@ namespace
template <typename T>
void range_function(ITensor *output, float start, float step, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector<T, wrapper::traits::BitWidth::W128>::tag_type;
const auto step_vec = wrapper::vdup_n(static_cast<T>(step), ExactTagType{});
@@ -189,4 +189,4 @@ void NERangeKernel::run(const Window &window, const ThreadInfo &info)
(*_func)(_output, _start, _step, window);
}
-} // namespace arm_compute \ No newline at end of file
+} // namespace arm_compute
diff --git a/src/core/NEON/kernels/NEReductionOperationKernel.cpp b/src/core/NEON/kernels/NEReductionOperationKernel.cpp
index 3d105cc60d..001025bdf5 100644
--- a/src/core/NEON/kernels/NEReductionOperationKernel.cpp
+++ b/src/core/NEON/kernels/NEReductionOperationKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -386,7 +386,7 @@ public:
template <typename T, int S>
struct RedOpX
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
inline void operator()(const Window &in_window, Window &out_window, const ITensor *in, ITensor *out, const ReductionOperation op)
@@ -859,7 +859,7 @@ struct RedOpX_quantized
template <typename T, int S>
struct RedOpYZW
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
using neon_vector = typename wrapper::traits::neon_vector<T, S>::type;
@@ -1078,7 +1078,7 @@ struct RedOpYZW
template <typename T, int S, int axis, ReductionOperation op>
struct RedOpYZW_complex
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
using neon_vector = typename wrapper::traits::neon_vector<T, S>::type;
diff --git a/src/core/NEON/kernels/NEReductionOperationKernel.h b/src/core/NEON/kernels/NEReductionOperationKernel.h
index dfc105adae..c7ed0070be 100644
--- a/src/core/NEON/kernels/NEReductionOperationKernel.h
+++ b/src/core/NEON/kernels/NEReductionOperationKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform a reduction operation
+/** Neon kernel to perform a reduction operation
*
* @note For ARG_MIN/ARG_MAX reduction, the default data type for an uninitialized
* output tensor is signed 32-bit integer (S32). It is the user's responsibility
diff --git a/src/core/NEON/kernels/NERemapKernel.h b/src/core/NEON/kernels/NERemapKernel.h
index 8fe1ba5855..adc7f4bdd5 100644
--- a/src/core/NEON/kernels/NERemapKernel.h
+++ b/src/core/NEON/kernels/NERemapKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -31,7 +31,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform a remap on a tensor */
+/** Neon kernel to perform a remap on a tensor */
class NERemapKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEReorgLayerKernel.cpp b/src/core/NEON/kernels/NEReorgLayerKernel.cpp
index 0dcb439665..215debe10f 100644
--- a/src/core/NEON/kernels/NEReorgLayerKernel.cpp
+++ b/src/core/NEON/kernels/NEReorgLayerKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -42,7 +42,7 @@ namespace
{
Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output, int32_t stride)
{
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON(input->data_layout() == DataLayout::UNKNOWN);
diff --git a/src/core/NEON/kernels/NEReverseKernel.cpp b/src/core/NEON/kernels/NEReverseKernel.cpp
index 21c758053a..b2fce0f56d 100644
--- a/src/core/NEON/kernels/NEReverseKernel.cpp
+++ b/src/core/NEON/kernels/NEReverseKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -37,7 +37,7 @@ namespace
Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output, const ITensorInfo *axis)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output, axis);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(axis, 1, DataType::U32);
ARM_COMPUTE_RETURN_ERROR_ON_MSG(axis->num_dimensions() > 1, "Axis must be a 1D tensor");
@@ -163,4 +163,4 @@ void NEReverseKernel::run(const Window &window, const ThreadInfo &info)
ARM_COMPUTE_ERROR("Element size not supported");
}
}
-} // namespace arm_compute \ No newline at end of file
+} // namespace arm_compute
diff --git a/src/core/NEON/kernels/NEScaleKernel.h b/src/core/NEON/kernels/NEScaleKernel.h
index f6ee3fa4c5..32fa8d7fb2 100644
--- a/src/core/NEON/kernels/NEScaleKernel.h
+++ b/src/core/NEON/kernels/NEScaleKernel.h
@@ -31,7 +31,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform scaling on a tensor */
+/** Neon kernel to perform scaling on a tensor */
class NEScaleKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEStackLayerKernel.cpp b/src/core/NEON/kernels/NEStackLayerKernel.cpp
index 55170a169a..64310e7f7f 100644
--- a/src/core/NEON/kernels/NEStackLayerKernel.cpp
+++ b/src/core/NEON/kernels/NEStackLayerKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -44,7 +44,7 @@ namespace
Status validate_arguments(const ITensorInfo *input, unsigned int axis, unsigned int idx_input, unsigned int num_tensors, const ITensorInfo *output)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output);
- // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON(idx_input >= num_tensors);
ARM_COMPUTE_RETURN_ERROR_ON(axis > input->num_dimensions());
diff --git a/src/core/NEON/kernels/NEStackLayerKernel.h b/src/core/NEON/kernels/NEStackLayerKernel.h
index 9b0a039b88..dc5c7d77ad 100644
--- a/src/core/NEON/kernels/NEStackLayerKernel.h
+++ b/src/core/NEON/kernels/NEStackLayerKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to stacks a rank-R tensor into one with rank-(R+1) along the axis dimension.*/
+/** Neon kernel to stacks a rank-R tensor into one with rank-(R+1) along the axis dimension.*/
class NEStackLayerKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NEThresholdKernel.cpp b/src/core/NEON/kernels/NEThresholdKernel.cpp
index 183bb8db5c..108f29f377 100644
--- a/src/core/NEON/kernels/NEThresholdKernel.cpp
+++ b/src/core/NEON/kernels/NEThresholdKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020 Arm Limited.
+ * Copyright (c) 2016-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -112,7 +112,7 @@ Status NEThresholdKernel::validate(const ITensorInfo *input, const ITensorInfo *
inline void NEThresholdKernel::run_binary(const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using Type = uint8_t;
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<Type, wrapper::traits::BitWidth::W128>;
@@ -158,7 +158,7 @@ inline void NEThresholdKernel::run_binary(const Window &window)
inline void NEThresholdKernel::run_range(const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using Type = uint8_t;
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<Type, wrapper::traits::BitWidth::W128>;
diff --git a/src/core/NEON/kernels/NETileKernel.h b/src/core/NEON/kernels/NETileKernel.h
index 8dfea8bc2f..e6ce9534e7 100644
--- a/src/core/NEON/kernels/NETileKernel.h
+++ b/src/core/NEON/kernels/NETileKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform a tile operation */
+/** Neon kernel to perform a tile operation */
class NETileKernel : public INEKernel
{
public:
diff --git a/src/core/NEON/kernels/NETransposeKernel.cpp b/src/core/NEON/kernels/NETransposeKernel.cpp
index 134831be4c..980d90b476 100644
--- a/src/core/NEON/kernels/NETransposeKernel.cpp
+++ b/src/core/NEON/kernels/NETransposeKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -59,7 +59,7 @@ TensorShape transposed_tensor_shape(const TensorShape &in)
Status validate_arguments(const ITensorInfo *input, const ITensorInfo *output)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
if(output->total_size() != 0)
@@ -125,7 +125,7 @@ void transpose_8bit_elements(const ITensor *in, ITensor *out, const Window &wind
Iterator output(out, window_out);
- // Run the NEON path if and only if the input is not a row-vector
+ // Run the Neon path if and only if the input is not a row-vector
if(in->info()->dimension(1) != 1)
{
Iterator input(in, window_in);
@@ -264,7 +264,7 @@ void transpose_16bit_elements(const ITensor *in, ITensor *out, const Window &win
Iterator output(out, window_out);
- // Run the NEON path if and only if the input is not a row-vector
+ // Run the Neon path if and only if the input is not a row-vector
if(in->info()->dimension(1) != 1)
{
Iterator input(in, window_in);
@@ -377,7 +377,7 @@ void transpose_32bit_elements(const ITensor *in, ITensor *out, const Window &win
Iterator output(out, window_out);
- // Run the NEON path if and only if the input is not a row-vector
+ // Run the Neon path if and only if the input is not a row-vector
if(in->info()->dimension(1) != 1)
{
Iterator input(in, window_in);
diff --git a/src/core/NEON/kernels/NETransposeKernel.h b/src/core/NEON/kernels/NETransposeKernel.h
index 73d2098fb3..88ece547e1 100644
--- a/src/core/NEON/kernels/NETransposeKernel.h
+++ b/src/core/NEON/kernels/NETransposeKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel which transposes the elements of a matrix.
+/** Neon kernel which transposes the elements of a matrix.
*
* [width, height, batch] -> [height, width, batch]
*
diff --git a/src/core/NEON/kernels/NEWeightsReshapeKernel.cpp b/src/core/NEON/kernels/NEWeightsReshapeKernel.cpp
index 118655b755..109652fb97 100644
--- a/src/core/NEON/kernels/NEWeightsReshapeKernel.cpp
+++ b/src/core/NEON/kernels/NEWeightsReshapeKernel.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -47,7 +47,7 @@ TensorShape get_output_shape(const ITensorInfo *input, bool has_bias)
Status validate_arguments(const ITensorInfo *input, const ITensorInfo *biases, const ITensorInfo *output)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(input->data_type() == DataType::UNKNOWN);
if(biases != nullptr)
diff --git a/src/core/NEON/kernels/NEWeightsReshapeKernel.h b/src/core/NEON/kernels/NEWeightsReshapeKernel.h
index 9678b79fda..a4a9e28763 100644
--- a/src/core/NEON/kernels/NEWeightsReshapeKernel.h
+++ b/src/core/NEON/kernels/NEWeightsReshapeKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@ namespace arm_compute
{
class ITensor;
-/** NEON kernel to perform reshaping on the weights used by convolution and locally connected layer
+/** Neon kernel to perform reshaping on the weights used by convolution and locally connected layer
*
* Rearranges each 3-dimensional kernel to a single row leading to a matrix with linearized kernels.
* In combination with the @ref NEIm2ColKernel can transform a convolution to a matrix multiplication.
diff --git a/src/core/NEON/kernels/NEWinogradConvolutionLayerKernel.h b/src/core/NEON/kernels/NEWinogradConvolutionLayerKernel.h
index 2b87e512dc..3583735482 100644
--- a/src/core/NEON/kernels/NEWinogradConvolutionLayerKernel.h
+++ b/src/core/NEON/kernels/NEWinogradConvolutionLayerKernel.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -35,7 +35,7 @@ namespace arm_compute
// Forward declarations
class ITensor;
-/** Interface for the NEON kernel to perform Winograd input transform. */
+/** Interface for the Neon kernel to perform Winograd input transform. */
class INEWinogradLayerTransformInputKernel : public INEKernel
{
public:
@@ -96,7 +96,7 @@ public:
}
};
-/** NEON kernel to perform Winograd input transform. */
+/** Neon kernel to perform Winograd input transform. */
template <typename T, int OutputTileRows, int OutputTileCols, int KernelRows, int KernelCols>
class NEWinogradLayerTransformInputKernel : public INEWinogradLayerTransformInputKernel
{
@@ -227,7 +227,7 @@ private:
ITensor *_workspace;
};
-/** Interface for the NEON kernel to perform Winograd output transform. */
+/** Interface for the Neon kernel to perform Winograd output transform. */
class INEWinogradLayerTransformOutputKernel : public INEKernel
{
public:
@@ -310,7 +310,7 @@ public:
}
};
-/** NEON kernel to perform Winograd output transform. */
+/** Neon kernel to perform Winograd output transform. */
template <typename T, int OutputTileRows, int OutputTileCols, int KernelRows, int KernelCols>
class NEWinogradLayerTransformOutputKernel : public INEWinogradLayerTransformOutputKernel
{
@@ -437,7 +437,7 @@ private:
int _num_channels;
};
-/** Interface for the NEON kernel to perform Winograd weights transform. */
+/** Interface for the Neon kernel to perform Winograd weights transform. */
class INEWinogradLayerTransformWeightsKernel : public INEKernel
{
public:
@@ -495,7 +495,7 @@ public:
static Status validate(const ITensorInfo *input, const ITensorInfo *weights);
};
-/** NEON kernel to perform Winograd weights transform. */
+/** Neon kernel to perform Winograd weights transform. */
template <typename T, int OutputTileRows, int OutputTileCols, int KernelRows, int KernelCols>
class NEWinogradLayerTransformWeightsKernel final : public INEWinogradLayerTransformWeightsKernel
{
@@ -577,7 +577,7 @@ private:
int _num_input_channels;
};
-/** NEON kernel to perform Winograd. */
+/** Neon kernel to perform Winograd. */
template <typename TIn, typename TOut, int OutputTileRows, int OutputTileCols, int KernelRows, int KernelCols>
class NEWinogradLayerConfiguration
{
diff --git a/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp b/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp
index c1e34d12f7..b0e912d188 100644
--- a/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp
+++ b/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp
@@ -111,7 +111,7 @@ static const GemmImplementation<float, float> gemm_fp32_methods[] =
},
#endif // __ARM_FEATURE_SVE
-// NEON hybrid methods
+// Neon hybrid methods
{
GemmMethod::GEMM_HYBRID,
"a64_smallK_hybrid_fp32_mla_8x4",
diff --git a/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp b/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp
index 02d9486cc6..bb86d9e41d 100644
--- a/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp
+++ b/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp
@@ -292,21 +292,21 @@ void Interleave(TOut *out, const TIn *in, size_t in_stride, const unsigned int y
/* AArch32 */
#ifdef __arm__
/* FP32 */
-/* NEON implementation (height 6) */
+/* Neon implementation (height 6) */
template void IndirectInterleave<6, 1, VLType::None>(float *, const float * const * const *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void ConvolutionInterleave<6, 1, VLType::None>(float *, const float *, size_t, const convolver<float> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<6, 1, VLType::None>(float *, const float *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
/* FP16 */
#if __ARM_FP16_ARGS
-/* NEON implementation using FP32 kernel (height 6) */
+/* Neon implementation using FP32 kernel (height 6) */
template void IndirectInterleave<6, 1, VLType::None>(float *, const __fp16 * const * const *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void ConvolutionInterleave<6, 1, VLType::None>(float *, const __fp16 *, size_t, const convolver<__fp16> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<6, 1, VLType::None>(float *, const __fp16 *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
#endif /* __ARM_FP16_ARGS */
/* BF16 */
-/* NEON implementation using FP32 kernel */
+/* Neon implementation using FP32 kernel */
template void IndirectInterleave<6, 1, VLType::None>(float *, const bfloat16 * const * const *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void ConvolutionInterleave<6, 1, VLType::None>(float *, const bfloat16 *, size_t, const convolver<bfloat16> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<6, 1, VLType::None>(float *, const bfloat16 *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
@@ -315,7 +315,7 @@ template void Interleave<6, 1, VLType::None>(float *, const bfloat16 *, size_t,
/* AArch64 */
#ifdef __aarch64__
/* FP32 */
-/* NEON/SVE implementation (height 8) */
+/* Neon/SVE implementation (height 8) */
template void IndirectInterleave<8, 1, VLType::None>(float *, const float * const * const *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void ConvolutionInterleave<8, 1, VLType::None>(float *, const float *, size_t, const convolver<float> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<8, 1, VLType::None>(float *, const float *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
@@ -339,7 +339,7 @@ template void ConvolutionInterleave<8, 1, VLType::None>(float *, const __fp16 *,
template void Interleave<8, 1, VLType::None>(float *, const __fp16 *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
/* BF16 */
-/* NEON/SVE BFDOT */
+/* Neon/SVE BFDOT */
#ifdef V8P6_BF
template void IndirectInterleave<8, 2, VLType::None>(bfloat16 *, const bfloat16 * const * const *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void ConvolutionInterleave<8, 2, VLType::None>(bfloat16 *, const bfloat16 *, size_t, const convolver<bfloat16> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
@@ -350,7 +350,7 @@ template void ConvolutionInterleave<8, 4, VLType::None>(bfloat16 *, const bfloat
template void Interleave<8, 4, VLType::None>(bfloat16 *, const bfloat16 *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
#endif // V8P6_BF
-/* NEON/SVE using FP32 kernel */
+/* Neon/SVE using FP32 kernel */
template void IndirectInterleave<8, 1, VLType::None>(float *, const bfloat16 * const * const *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void ConvolutionInterleave<8, 1, VLType::None>(float *, const bfloat16 *, size_t, const convolver<bfloat16> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<8, 1, VLType::None>(float *, const bfloat16 *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
@@ -365,12 +365,12 @@ template void ConvolutionInterleave<8, 1, VLType::None>(uint16_t *, const uint16
template void Interleave<8, 1, VLType::None>(uint16_t *, const uint16_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
/* INT8 */
-/* NEON SMLA/SMLAL (height 4, block 16) */
+/* Neon SMLA/SMLAL (height 4, block 16) */
template void IndirectInterleave<4, 16, VLType::None>(int8_t *, const int8_t * const * const *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void ConvolutionInterleave<4, 16, VLType::None>(int8_t *, const int8_t *, size_t, const convolver<int8_t> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<4, 16, VLType::None>(int8_t *, const int8_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
-/* NEON SDOT (height 8, block 4) */
+/* Neon SDOT (height 8, block 4) */
template void IndirectInterleave<8, 4, VLType::None>(int8_t *, const int8_t * const * const *, unsigned int, unsigned int, unsigned int y0, unsigned int ymax, unsigned int k0, unsigned int kmax, bool, int32_t);
template void ConvolutionInterleave<8, 4, VLType::None>(int8_t *, const int8_t *, size_t, const convolver<int8_t> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<8, 4, VLType::None>(int8_t *, const int8_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
@@ -382,17 +382,17 @@ template void ConvolutionInterleave<8, 8, VLType::None>(int8_t *, const int8_t *
template void Interleave<8, 8, VLType::None>(int8_t *, const int8_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
#endif // MMLA_INT8
-/* NEON SDOT (height 8, block 1) */
+/* Neon SDOT (height 8, block 1) */
template void IndirectInterleave<8, 1, VLType::None>(int16_t *, const int8_t * const * const *, unsigned int, unsigned int, unsigned int y0, unsigned int ymax, unsigned int k0, unsigned int kmax, bool, int32_t);
template void ConvolutionInterleave<8, 1, VLType::None>(int16_t *, const int8_t *, size_t, const convolver<int8_t> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<8, 1, VLType::None>(int16_t *, const int8_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
-/* NEON SMLA/SMLAL (height 4, block 16) */
+/* Neon SMLA/SMLAL (height 4, block 16) */
template void IndirectInterleave<4, 16, VLType::None>(uint8_t *, const uint8_t * const * const *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void ConvolutionInterleave<4, 16, VLType::None>(uint8_t *, const uint8_t *, size_t, const convolver<uint8_t> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<4, 16, VLType::None>(uint8_t *, const uint8_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
-/* NEON SDOT (height 8, block 4) */
+/* Neon SDOT (height 8, block 4) */
template void IndirectInterleave<8, 4, VLType::None>(uint8_t *, const uint8_t * const * const *, unsigned int, unsigned int, unsigned int y0, unsigned int ymax, unsigned int k0, unsigned int kmax, bool, int32_t);
template void ConvolutionInterleave<8, 4, VLType::None>(uint8_t *, const uint8_t *, size_t, const convolver<uint8_t> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<8, 4, VLType::None>(uint8_t *, const uint8_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
@@ -404,7 +404,7 @@ template void ConvolutionInterleave<8, 8, VLType::None>(uint8_t *, const uint8_t
template void Interleave<8, 8, VLType::None>(uint8_t *, const uint8_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
#endif // MMLA_INT8
-/* NEON 16-bit (height 8, block 1) */
+/* Neon 16-bit (height 8, block 1) */
template void IndirectInterleave<8, 1, VLType::None>(uint16_t *, const uint8_t * const * const *, unsigned int, unsigned int, unsigned int y0, unsigned int ymax, unsigned int k0, unsigned int kmax, bool, int32_t);
template void ConvolutionInterleave<8, 1, VLType::None>(uint16_t *, const uint8_t *, size_t, const convolver<uint8_t> &, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
template void Interleave<8, 1, VLType::None>(uint16_t *, const uint8_t *, size_t, unsigned int, unsigned int, unsigned int, unsigned int, bool, int32_t);
diff --git a/src/core/NEON/kernels/batchnormalization/impl/NEON/fp16.cpp b/src/core/NEON/kernels/batchnormalization/impl/NEON/fp16.cpp
index 704f003521..4108d79a5a 100644
--- a/src/core/NEON/kernels/batchnormalization/impl/NEON/fp16.cpp
+++ b/src/core/NEON/kernels/batchnormalization/impl/NEON/fp16.cpp
@@ -45,7 +45,7 @@ template <typename T>
void batch_normalization(ITensor *src, ITensor *dst, const ITensor *mean, const ITensor *var, const ITensor *beta, const ITensor *gamma,
float epsilon, ActivationLayerInfo &act_info, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<float16_t, wrapper::traits::BitWidth::W128>;
const int window_step_x = 8;
@@ -149,4 +149,4 @@ void fp16_neon_batch_normalization(ITensor *src, ITensor *dst, const ITensor *me
} // namespace cpu
} // namespace arm_compute
-#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ \ No newline at end of file
+#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */
diff --git a/src/core/NEON/kernels/batchnormalization/impl/NEON/fp32.cpp b/src/core/NEON/kernels/batchnormalization/impl/NEON/fp32.cpp
index 76a71ed738..1fdc5bd5b1 100644
--- a/src/core/NEON/kernels/batchnormalization/impl/NEON/fp32.cpp
+++ b/src/core/NEON/kernels/batchnormalization/impl/NEON/fp32.cpp
@@ -44,7 +44,7 @@ template <typename T>
void batch_normalization(ITensor *src, ITensor *dst, const ITensor *mean, const ITensor *var, const ITensor *beta, const ITensor *gamma,
float epsilon, ActivationLayerInfo &act_info, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<float, wrapper::traits::BitWidth::W128>;
const int window_step_x = 4;
diff --git a/src/core/NEON/kernels/detail/NEActivationFunctionDetail.h b/src/core/NEON/kernels/detail/NEActivationFunctionDetail.h
index eef1be06eb..e68f1117e8 100644
--- a/src/core/NEON/kernels/detail/NEActivationFunctionDetail.h
+++ b/src/core/NEON/kernels/detail/NEActivationFunctionDetail.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -34,7 +34,7 @@ namespace detail
template <typename T, int S>
struct dummy
{
- /** NEON vector type. */
+ /** Neon vector type. */
using ExactType = typename wrapper::traits::neon_vector<T, S>::type;
/** Construct a dummy activation object.
@@ -68,9 +68,9 @@ struct dummy
template <typename T, int S>
struct linear
{
- /** NEON vector type. */
+ /** Neon vector type. */
using ExactType = typename wrapper::traits::neon_vector<T, S>::type;
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
/** Construct a Linear activation object.
@@ -112,9 +112,9 @@ struct linear
template <typename T, int S>
struct square
{
- /** NEON vector type. */
+ /** Neon vector type. */
using ExactType = typename wrapper::traits::neon_vector<T, S>::type;
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
/** Construct a Square activation object.
@@ -148,9 +148,9 @@ struct square
template <typename T, int S>
struct logistic
{
- /** NEON vector type. */
+ /** Neon vector type. */
using ExactType = typename wrapper::traits::neon_vector<T, S>::type;
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
/** Construct a Logistic activation object.
@@ -188,9 +188,9 @@ struct logistic
template <typename T, int S>
struct relu
{
- /** NEON vector type. */
+ /** Neon vector type. */
using ExactType = typename wrapper::traits::neon_vector<T, S>::type;
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
/** Construct a RELU activation object.
@@ -228,9 +228,9 @@ struct relu
template <typename T, int S>
struct brelu
{
- /** NEON vector type. */
+ /** Neon vector type. */
using ExactType = typename wrapper::traits::neon_vector<T, S>::type;
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
/** Construct a bounded RELU activation object.
@@ -270,9 +270,9 @@ struct brelu
template <typename T, int S>
struct lubrelu
{
- /** NEON vector type. */
+ /** Neon vector type. */
using ExactType = typename wrapper::traits::neon_vector<T, S>::type;
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_vector<T, S>::tag_type;
/** Construct a lower-upper bounded RELU activation object.
diff --git a/src/core/NEON/wrapper/traits.h b/src/core/NEON/wrapper/traits.h
index 0bb55afe02..b786e44bc7 100644
--- a/src/core/NEON/wrapper/traits.h
+++ b/src/core/NEON/wrapper/traits.h
@@ -44,7 +44,7 @@ struct vector_64_tag {};
/** 128-bit vector tag */
struct vector_128_tag {};
-/** Create the appropriate NEON vector given its type and size in terms of elements */
+/** Create the appropriate Neon vector given its type and size in terms of elements */
template <typename T, int S> struct neon_vector;
// Specializations
@@ -88,7 +88,7 @@ enum class BitWidth
W128, /**< 128-bit width */
};
-/** Create the appropriate NEON vector given its type and size in terms of bits */
+/** Create the appropriate Neon vector given its type and size in terms of bits */
template <typename T, BitWidth BW> struct neon_bitvector;
// Specializations
#ifndef DOXYGEN_SKIP_THIS
diff --git a/src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp b/src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp
index e51c341851..48eac13041 100644
--- a/src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp
+++ b/src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp
@@ -133,7 +133,7 @@ void batch_concat(const ITensor *src, ITensor *dst, unsigned int batch_offset, c
Status validate_arguments(const ITensorInfo *src, unsigned int batch_offset, const ITensorInfo *dst)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(src->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst);
diff --git a/src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp b/src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp
index dee0283a2c..f64c282ae4 100644
--- a/src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp
+++ b/src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp
@@ -134,7 +134,7 @@ void depth_concat(const ITensor *src, ITensor *dst, unsigned int depth_offset, c
Status validate_arguments(const ITensorInfo *input, unsigned int depth_offset, const ITensorInfo *output)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output);
- //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::F16, DataType::F32);
ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(input, output);
diff --git a/src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp b/src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp
index 8522c93340..c6e224970a 100644
--- a/src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp
+++ b/src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp
@@ -49,7 +49,7 @@ namespace
Status validate_arguments(const ITensorInfo *src, unsigned int height_offset, const ITensorInfo *dst)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst);
- // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(src->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst);
ARM_COMPUTE_RETURN_ERROR_ON(src->dimension(Window::DimX) != dst->dimension(Window::DimX));
diff --git a/src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp b/src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp
index 27ded05aff..e707e8d5a4 100644
--- a/src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp
+++ b/src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp
@@ -49,7 +49,7 @@ namespace
Status validate_arguments(const ITensorInfo *src, unsigned int width_offset, const ITensorInfo *dst)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst);
- // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(src->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst);
ARM_COMPUTE_RETURN_ERROR_ON(src->dimension(0) + width_offset > dst->dimension(0));
diff --git a/src/core/cpu/kernels/CpuReshapeKernel.cpp b/src/core/cpu/kernels/CpuReshapeKernel.cpp
index 068f5d025b..41ff8bd390 100644
--- a/src/core/cpu/kernels/CpuReshapeKernel.cpp
+++ b/src/core/cpu/kernels/CpuReshapeKernel.cpp
@@ -50,7 +50,7 @@ namespace
Status validate_arguments(const ITensorInfo *src, const ITensorInfo *dst)
{
ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst);
- // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use NEON FP16 instructions.
+ // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use Neon FP16 instructions.
ARM_COMPUTE_RETURN_ERROR_ON(src->data_type() == DataType::UNKNOWN);
ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst);
diff --git a/src/core/cpu/kernels/activation/NEON/fp16.cpp b/src/core/cpu/kernels/activation/NEON/fp16.cpp
index bd459e9e77..7fe4ab3f63 100644
--- a/src/core/cpu/kernels/activation/NEON/fp16.cpp
+++ b/src/core/cpu/kernels/activation/NEON/fp16.cpp
@@ -51,7 +51,7 @@ inline float16x8_t mask_float_vector(const float16x8_t &in, const uint16x8_t &ma
void fp16_neon_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<float16_t, wrapper::traits::BitWidth::W128>;
const ActivationLayerInfo::ActivationFunction act = act_info.activation();
@@ -215,4 +215,4 @@ void fp16_neon_activation(const ITensor *src, ITensor *dst, const ActivationLaye
} // namespace cpu
} // namespace arm_compute
-#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ \ No newline at end of file
+#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */
diff --git a/src/core/cpu/kernels/activation/NEON/fp32.cpp b/src/core/cpu/kernels/activation/NEON/fp32.cpp
index c76035b5d2..f1f2753813 100644
--- a/src/core/cpu/kernels/activation/NEON/fp32.cpp
+++ b/src/core/cpu/kernels/activation/NEON/fp32.cpp
@@ -49,7 +49,7 @@ inline float32x4_t mask_float_vector(const float32x4_t &in, const uint32x4_t &ma
void fp32_neon_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename arm_compute::wrapper::traits::neon_bitvector_tag_t<float, wrapper::traits::BitWidth::W128>;
constexpr int window_step_x = 4;
diff --git a/src/core/cpu/kernels/add/neon/list.h b/src/core/cpu/kernels/add/neon/list.h
index 53ea81e284..964bdccca3 100644
--- a/src/core/cpu/kernels/add/neon/list.h
+++ b/src/core/cpu/kernels/add/neon/list.h
@@ -47,7 +47,7 @@ DECLARE_ADD_KERNEL(add_u8_u8_s16_neon);
template <typename ScalarType>
void add_same_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<ScalarType, wrapper::traits::BitWidth::W128>;
// Create input windows
@@ -143,4 +143,4 @@ void add_same_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const
}
} // namespace cpu
} // namespace arm_compute
-#endif // SRC_CORE_NEON_KERNELS_ADD_LIST_H \ No newline at end of file
+#endif // SRC_CORE_NEON_KERNELS_ADD_LIST_H
diff --git a/src/core/cpu/kernels/pooling/neon/quantized.h b/src/core/cpu/kernels/pooling/neon/quantized.h
index 81fb777ef2..535fb53d87 100644
--- a/src/core/cpu/kernels/pooling/neon/quantized.h
+++ b/src/core/cpu/kernels/pooling/neon/quantized.h
@@ -473,7 +473,7 @@ void pooling2_quantized_neon_nchw(const ITensor *src, ITensor *dst0, ITensor *ds
Iterator in(src, window_src);
Iterator out(dst0, window);
- /** NEON vector types */
+ /** Neon vector types */
using q8x8_t = typename wrapper::traits::neon_vector<T, 8>::type;
using q8x16_t = typename wrapper::traits::neon_vector<T, 16>::type;
using q8x8x2_t = typename std::conditional<std::is_same<T, uint8_t>::value, uint8x8x2_t, int8x8x2_t>::type;
@@ -602,7 +602,7 @@ void pooling3_quantized_neon_nchw(const ITensor *src, ITensor *dst0, ITensor *ds
Iterator in(src, window_src);
Iterator out(dst0, window);
- /** NEON vector types */
+ /** Neon vector types */
using q8x8_t = typename wrapper::traits::neon_vector<T, 8>::type;
using q8x16_t = typename wrapper::traits::neon_vector<T, 16>::type;
using q8x8x2_t = typename std::conditional<std::is_same<T, uint8_t>::value, uint8x8x2_t, int8x8x2_t>::type;
@@ -756,7 +756,7 @@ void poolingMxN_quantized_neon_nchw(const ITensor *src, ITensor *dst0, ITensor *
Iterator in(src, window_src);
Iterator out(dst0, window);
- /** NEON vector types */
+ /** Neon vector types */
using q8x8_t = typename wrapper::traits::neon_vector<T, 8>::type;
using q16_t = typename wrapper::traits::promote_t<T>;
using q16x8_t = typename wrapper::traits::neon_vector<q16_t, 8>::type;
@@ -860,4 +860,4 @@ void poolingMxN_quantized_neon_nchw(const ITensor *src, ITensor *dst0, ITensor *
} // namespace cpu
} // namespace arm_compute
-#endif // SRC_CORE_NEON_KERNELS_QUANTIZED_H \ No newline at end of file
+#endif // SRC_CORE_NEON_KERNELS_QUANTIZED_H
diff --git a/src/core/cpu/kernels/softmax/impl/NEON/list.h b/src/core/cpu/kernels/softmax/impl/NEON/list.h
index 1aa7e8fac7..3f9438e0c7 100644
--- a/src/core/cpu/kernels/softmax/impl/NEON/list.h
+++ b/src/core/cpu/kernels/softmax/impl/NEON/list.h
@@ -73,7 +73,7 @@ float32x4x4_t convert_int_to_float<float32x4x4_t, int8x16_t>(const int8x16_t &in
template <typename T>
void neon_logits_1d_max(const ITensor *in, ITensor *out, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<T, wrapper::traits::BitWidth::W128>;
constexpr int window_step_x = 16 / sizeof(T);
@@ -304,7 +304,7 @@ void neon_softmax_logits_1d_float(const ITensor *in, const ITensor *max, void *c
Iterator max_it(max, window);
Iterator out_it(out, window);
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<T, wrapper::traits::BitWidth::W128>;
constexpr int vec_size = 16 / sizeof(T);
diff --git a/src/core/cpu/kernels/sub/neon/list.h b/src/core/cpu/kernels/sub/neon/list.h
index d5685824fc..8c82402513 100644
--- a/src/core/cpu/kernels/sub/neon/list.h
+++ b/src/core/cpu/kernels/sub/neon/list.h
@@ -47,7 +47,7 @@ DECLARE_SUB_KERNEL(sub_u8_u8_s16_neon);
template <typename T>
void sub_same_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
{
- /** NEON vector tag type. */
+ /** Neon vector tag type. */
using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t<T, wrapper::traits::BitWidth::W128>;
bool is_sat = policy == ConvertPolicy::SATURATE;
@@ -159,4 +159,4 @@ void sub_same_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const
}
} // namespace cpu
} // namespace arm_compute
-#endif // SRC_CORE_NEON_KERNELS_SUB_LIST_H \ No newline at end of file
+#endif // SRC_CORE_NEON_KERNELS_SUB_LIST_H
diff --git a/src/graph/backends/NEON/NEDeviceBackend.cpp b/src/graph/backends/NEON/NEDeviceBackend.cpp
index 7f87710cf3..a6c4fe9aa3 100644
--- a/src/graph/backends/NEON/NEDeviceBackend.cpp
+++ b/src/graph/backends/NEON/NEDeviceBackend.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@ namespace graph
{
namespace backends
{
-/** Register NEON backend */
+/** Register Neon backend */
static detail::BackendRegistrar<NEDeviceBackend> NEDeviceBackend_registrar(Target::NEON);
NEDeviceBackend::NEDeviceBackend()
@@ -138,7 +138,7 @@ std::unique_ptr<ITensorHandle> NEDeviceBackend::create_subtensor(ITensorHandle *
std::unique_ptr<arm_compute::IFunction> NEDeviceBackend::configure_node(INode &node, GraphContext &ctx)
{
- ARM_COMPUTE_LOG_GRAPH_VERBOSE("Configuring NEON node with ID : " << node.id() << std::endl);
+ ARM_COMPUTE_LOG_GRAPH_VERBOSE("Configuring Neon node with ID : " << node.id() << std::endl);
ARM_COMPUTE_ERROR_ON(node.assigned_target() != Target::NEON);
// Configure node
@@ -147,7 +147,7 @@ std::unique_ptr<arm_compute::IFunction> NEDeviceBackend::configure_node(INode &n
arm_compute::Status NEDeviceBackend::validate_node(INode &node)
{
- ARM_COMPUTE_LOG_GRAPH_VERBOSE("Validating NEON node with ID : " << node.id() << std::endl);
+ ARM_COMPUTE_LOG_GRAPH_VERBOSE("Validating Neon node with ID : " << node.id() << std::endl);
ARM_COMPUTE_ERROR_ON(node.assigned_target() != Target::NEON);
return NENodeValidator::validate(&node);
diff --git a/src/graph/backends/NEON/NEFunctionFactory.cpp b/src/graph/backends/NEON/NEFunctionFactory.cpp
index 83954b6307..6cf5874633 100644
--- a/src/graph/backends/NEON/NEFunctionFactory.cpp
+++ b/src/graph/backends/NEON/NEFunctionFactory.cpp
@@ -54,7 +54,7 @@ struct NETargetInfo
Target NETargetInfo::TargetType = Target::NEON;
-/** Collection of NEON convolution functions */
+/** Collection of Neon convolution functions */
struct NEConvolutionLayerFunctions
{
using GenericConvolutionLayer = NEConvolutionLayer;
@@ -63,7 +63,7 @@ struct NEConvolutionLayerFunctions
using WinogradConvolutionLayer = NEWinogradConvolutionLayer;
};
-/** Collection of NEON element-wise functions */
+/** Collection of Neon element-wise functions */
struct NEEltwiseFunctions
{
using Addition = NEArithmeticAddition;
@@ -73,13 +73,13 @@ struct NEEltwiseFunctions
using Division = NEElementwiseDivision;
};
-/** Collection of NEON unary element-wise functions */
+/** Collection of Neon unary element-wise functions */
struct NEUnaryEltwiseFunctions
{
using Exp = NEExpLayer;
};
-/** Function and tensor types to be used inside a NEON fused convolution/batch normalization layer */
+/** Function and tensor types to be used inside a Neon fused convolution/batch normalization layer */
struct NEFusedLayerTypes
{
using ConvolutionLayer = NEConvolutionLayer;
diff --git a/src/graph/backends/NEON/NENodeValidator.cpp b/src/graph/backends/NEON/NENodeValidator.cpp
index 3fb79dbfc0..8453cfa03a 100644
--- a/src/graph/backends/NEON/NENodeValidator.cpp
+++ b/src/graph/backends/NEON/NENodeValidator.cpp
@@ -50,7 +50,7 @@ namespace graph
{
namespace backends
{
-/** Collection of NEON element-wise functions */
+/** Collection of Neon element-wise functions */
struct NEEltwiseLayerFunctions
{
using ArithmeticAddition = NEArithmeticAddition;
@@ -60,7 +60,7 @@ struct NEEltwiseLayerFunctions
using ArithmeticDivision = NEElementwiseDivision;
};
-/** Collection of NEON unary element-wise functions */
+/** Collection of Neon unary element-wise functions */
struct NEUnaryEltwiseLayerFunctions
{
using ExpLayer = NEExpLayer;
diff --git a/src/runtime/NEON/functions/NEConvolutionLayer.cpp b/src/runtime/NEON/functions/NEConvolutionLayer.cpp
index cc549ca31b..e43d976944 100644
--- a/src/runtime/NEON/functions/NEConvolutionLayer.cpp
+++ b/src/runtime/NEON/functions/NEConvolutionLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -101,7 +101,7 @@ void NEConvolutionLayer::configure(ITensor *input, const ITensor *weights, const
Status NEConvolutionLayer::validate(const ITensorInfo *input, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *output, const PadStrideInfo &conv_info,
const WeightsInfo &weights_info, const Size2D &dilation, const ActivationLayerInfo &act_info, bool enable_fast_math, unsigned int num_groups)
{
- ARM_COMPUTE_RETURN_ERROR_ON_MSG((num_groups != 1), "Grouping (num_groups != 1) is not supported on NEON");
+ ARM_COMPUTE_RETURN_ERROR_ON_MSG((num_groups != 1), "Grouping (num_groups != 1) is not supported on Neon");
const Conv2dInfo info(conv_info, dilation, act_info, enable_fast_math, num_groups);
switch(NEConvolutionLayer::get_convolution_method(input, weights, output, conv_info, weights_info, dilation, act_info, enable_fast_math))
diff --git a/src/runtime/NEON/functions/NEGEMMAssemblyDispatch.cpp b/src/runtime/NEON/functions/NEGEMMAssemblyDispatch.cpp
index 0fd21edee1..8114adadc2 100644
--- a/src/runtime/NEON/functions/NEGEMMAssemblyDispatch.cpp
+++ b/src/runtime/NEON/functions/NEGEMMAssemblyDispatch.cpp
@@ -285,7 +285,7 @@ private:
/** Assembly Gemm kernel */
std::shared_ptr<arm_gemm::GemmCommon<TypeInput, TypeOutput>> _gemm_kernel_asm{ nullptr };
- /** Optimised NEON kernel */
+ /** Optimised Neon kernel */
std::unique_ptr<INEKernel> _optimised_kernel{ nullptr };
/** Input A */
const ITensor *_a
diff --git a/src/runtime/NEON/functions/NEGEMMConv2d.cpp b/src/runtime/NEON/functions/NEGEMMConv2d.cpp
index b8349d98db..c802298f98 100644
--- a/src/runtime/NEON/functions/NEGEMMConv2d.cpp
+++ b/src/runtime/NEON/functions/NEGEMMConv2d.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -122,7 +122,7 @@ Status NEGEMMConv2d::validate(const ITensorInfo *input, const ITensorInfo *weigh
ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::BFLOAT16, DataType::F16, DataType::F32);
ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(weights, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::QSYMM8_PER_CHANNEL, DataType::BFLOAT16, DataType::F16, DataType::F32);
ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(input, weights);
- ARM_COMPUTE_RETURN_ERROR_ON_MSG(info.num_groups > 1, "Grouping (num_groups != 1) is not supported on NEON");
+ ARM_COMPUTE_RETURN_ERROR_ON_MSG(info.num_groups > 1, "Grouping (num_groups != 1) is not supported on Neon");
ARM_COMPUTE_RETURN_ERROR_ON_MSG(input->data_layout() != DataLayout::NHWC, "Data layout supported is NHWC");
const DataType data_type = input->data_type();
const TensorShape i_shape = input->tensor_shape();
diff --git a/src/runtime/NEON/functions/NEGEMMConvolutionLayer.cpp b/src/runtime/NEON/functions/NEGEMMConvolutionLayer.cpp
index 2d296f39ea..e623d9dc74 100644
--- a/src/runtime/NEON/functions/NEGEMMConvolutionLayer.cpp
+++ b/src/runtime/NEON/functions/NEGEMMConvolutionLayer.cpp
@@ -431,7 +431,7 @@ Status NEGEMMConvolutionLayer::validate(const ITensorInfo *input, const ITensorI
ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::BFLOAT16, DataType::F16, DataType::F32);
ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(weights, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::QSYMM8_PER_CHANNEL, DataType::BFLOAT16, DataType::F16, DataType::F32);
ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(input, weights);
- ARM_COMPUTE_RETURN_ERROR_ON_MSG(num_groups > 1, "Grouping (num_groups != 1) is not supported on NEON");
+ ARM_COMPUTE_RETURN_ERROR_ON_MSG(num_groups > 1, "Grouping (num_groups != 1) is not supported on Neon");
const DataLayout data_layout = input->data_layout();
const DataType data_type = input->data_type();
@@ -523,7 +523,7 @@ Status NEGEMMConvolutionLayer::validate(const ITensorInfo *input, const ITensorI
if(!skip_im2col)
{
// Create tensor info for im2col reshaped inputs
- // For NEON the batch size is on the fourth dimension
+ // For Neon the batch size is on the fourth dimension
// TODO (giaiod01): Auto-initialize the output shape of im2col COMPMID-1482
TensorShape shape_im2col = input->tensor_shape();
shape_im2col.set(0, mat_weights_rows);
diff --git a/src/runtime/cpu/operators/CpuPooling.h b/src/runtime/cpu/operators/CpuPooling.h
index aa607b4b44..9ebcd5f6aa 100644
--- a/src/runtime/cpu/operators/CpuPooling.h
+++ b/src/runtime/cpu/operators/CpuPooling.h
@@ -40,7 +40,7 @@ namespace cpu
{
// Forward Declarations
class CpuPoolingAssemblyDispatch;
-/** Basic function to simulate a pooling layer with the specified pooling operation. This function calls the following NEON kernels:
+/** Basic function to simulate a pooling layer with the specified pooling operation. This function calls the following Neon kernels:
*
* -# @ref NEFillBorderKernel (executed if padding size is different from zero)
* -# @ref kernels::CpuPoolingKernel
diff --git a/tests/benchmark/NEON/Scale.cpp b/tests/benchmark/NEON/Scale.cpp
index 7da1b892f7..85a9e68fee 100644
--- a/tests/benchmark/NEON/Scale.cpp
+++ b/tests/benchmark/NEON/Scale.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -55,7 +55,7 @@ REGISTER_FIXTURE_DATA_TEST_CASE(RunSmall, NEScaleFixture, framework::DatasetMode
datasets::BorderModes()),
framework::dataset::make("SamplingPolicy", { SamplingPolicy::CENTER })));
TEST_SUITE_END() // Scale
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace benchmark
} // namespace test
} // namespace arm_compute
diff --git a/tests/benchmark/fixtures/ScaleLayerFixture.h b/tests/benchmark/fixtures/ScaleLayerFixture.h
index f69b918f4a..a6a798f5b1 100644
--- a/tests/benchmark/fixtures/ScaleLayerFixture.h
+++ b/tests/benchmark/fixtures/ScaleLayerFixture.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -35,7 +35,7 @@ namespace arm_compute
{
namespace test
{
-/** Fixture that can be used for NEON, CL and OpenGL ES */
+/** Fixture that can be used for Neon, CL and OpenGL ES */
template <typename TensorType, typename Function, typename Accessor, typename T>
class ScaleLayerFixture : public framework::Fixture
{
diff --git a/tests/datasets/ScaleValidationDataset.h b/tests/datasets/ScaleValidationDataset.h
index 217876b28b..25112f155f 100644
--- a/tests/datasets/ScaleValidationDataset.h
+++ b/tests/datasets/ScaleValidationDataset.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -140,7 +140,7 @@ const auto ScaleAlignCornersSamplingPolicySet = combine(framework::dataset::make
}),
framework::dataset::make("AlignCorners", { true }));
-/** Generated shapes: Used by NEON precommit and nightly
+/** Generated shapes: Used by Neon precommit and nightly
* - 2D shapes with 0, 1, 2 vector iterations
* - 3D shapes with 0, 1 vector iterations
* - 4D shapes with 0 vector iterations
@@ -192,4 +192,4 @@ framework::dataset::make("AlignCorners", { true }));
} // namespace datasets
} // namespace test
} // namespace arm_compute
-#endif /* ARM_COMPUTE_TEST_SCALE_VALIDATION_DATASET */ \ No newline at end of file
+#endif /* ARM_COMPUTE_TEST_SCALE_VALIDATION_DATASET */
diff --git a/tests/framework/SConscript b/tests/framework/SConscript
index 0dae7560d6..0ac9f9e5a9 100644
--- a/tests/framework/SConscript
+++ b/tests/framework/SConscript
@@ -72,7 +72,7 @@ if not env['opencl']:
files = [f for f in files if "OpenCL" not in os.path.basename(str(f))]
if not framework_env['mali']:
- # Remove MALI files
+ # Remove Mali files
files = [f for f in files if "MaliCounter" not in os.path.basename(str(f))]
else:
framework_env.Append(CPPDEFINES = ['MALI_ENABLED'])
diff --git a/tests/validation/GLES_COMPUTE/Scale.cpp b/tests/validation/GLES_COMPUTE/Scale.cpp
index 0df3170e8b..8731f0bc80 100644
--- a/tests/validation/GLES_COMPUTE/Scale.cpp
+++ b/tests/validation/GLES_COMPUTE/Scale.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@ const auto ScaleDataTypes = framework::dataset::make("DataType",
DataType::F16,
});
-/** Aligned corners, this functionality is supported only by NEON and OpenCL backends */
+/** Aligned corners, this functionality is supported only by Neon and OpenCL backends */
const auto AlignCorners = framework::dataset::make("AlignCorners",
{
false,
diff --git a/tests/validation/NEON/AbsoluteDifference.cpp b/tests/validation/NEON/AbsoluteDifference.cpp
index b39023eead..09e3ebc378 100644
--- a/tests/validation/NEON/AbsoluteDifference.cpp
+++ b/tests/validation/NEON/AbsoluteDifference.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -86,7 +86,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEAbsoluteDifferenceFixture<int16_t>, framework
TEST_SUITE_END() // S16
TEST_SUITE_END() // AbsoluteDifference
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Accumulate.cpp b/tests/validation/NEON/Accumulate.cpp
index 2b5ebbb0e7..3718343a71 100644
--- a/tests/validation/NEON/Accumulate.cpp
+++ b/tests/validation/NEON/Accumulate.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -113,7 +113,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEAccumulateSquaredFixture<uint8_t>, framework:
TEST_SUITE_END() // U8
TEST_SUITE_END() // AccumulateSquared
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ActivationLayer.cpp b/tests/validation/NEON/ActivationLayer.cpp
index 456b96d0ea..577603d07d 100644
--- a/tests/validation/NEON/ActivationLayer.cpp
+++ b/tests/validation/NEON/ActivationLayer.cpp
@@ -335,7 +335,7 @@ TEST_SUITE_END() // QSYMM16
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // ActivationLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ArgMinMax.cpp b/tests/validation/NEON/ArgMinMax.cpp
index 6aa382d9b4..0a4071076a 100644
--- a/tests/validation/NEON/ArgMinMax.cpp
+++ b/tests/validation/NEON/ArgMinMax.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -188,7 +188,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge,
}
TEST_SUITE_END() // QASYMM8_SIGNED
TEST_SUITE_END() // ArgMinMax
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ArithmeticAddition.cpp b/tests/validation/NEON/ArithmeticAddition.cpp
index 5598a1106b..98341805ed 100644
--- a/tests/validation/NEON/ArithmeticAddition.cpp
+++ b/tests/validation/NEON/ArithmeticAddition.cpp
@@ -274,7 +274,7 @@ TEST_SUITE_END() // QSYMM16
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // ArithmeticAddition
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ArithmeticSubtraction.cpp b/tests/validation/NEON/ArithmeticSubtraction.cpp
index 12fe64c396..7a36893445 100644
--- a/tests/validation/NEON/ArithmeticSubtraction.cpp
+++ b/tests/validation/NEON/ArithmeticSubtraction.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -348,7 +348,7 @@ TEST_SUITE_END() // F32
TEST_SUITE_END() // Float
TEST_SUITE_END() // ArithmeticSubtraction
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/BatchNormalizationLayer.cpp b/tests/validation/NEON/BatchNormalizationLayer.cpp
index 5b2c83e9b5..a1ae6971f4 100644
--- a/tests/validation/NEON/BatchNormalizationLayer.cpp
+++ b/tests/validation/NEON/BatchNormalizationLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -220,7 +220,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // BatchNormalizationLayerFusion
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/BatchToSpaceLayer.cpp b/tests/validation/NEON/BatchToSpaceLayer.cpp
index ff78ce8fa4..a305dcbcc4 100644
--- a/tests/validation/NEON/BatchToSpaceLayer.cpp
+++ b/tests/validation/NEON/BatchToSpaceLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -140,7 +140,7 @@ TEST_SUITE_END()
TEST_SUITE_END()
TEST_SUITE_END() // BatchToSpace
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/BitwiseAnd.cpp b/tests/validation/NEON/BitwiseAnd.cpp
index 8796cc1147..eff649e87a 100644
--- a/tests/validation/NEON/BitwiseAnd.cpp
+++ b/tests/validation/NEON/BitwiseAnd.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -53,7 +53,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEBitwiseAndFixture<uint8_t>, framework::Datase
validate(Accessor(_target), _reference);
}
TEST_SUITE_END() // BitwiseAnd
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/BitwiseNot.cpp b/tests/validation/NEON/BitwiseNot.cpp
index 13b3e6d7f3..73b49b6ff1 100644
--- a/tests/validation/NEON/BitwiseNot.cpp
+++ b/tests/validation/NEON/BitwiseNot.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -53,7 +53,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEBitwiseNotFixture<uint8_t>, framework::Datase
validate(Accessor(_target), _reference);
}
TEST_SUITE_END() // BitwiseNot
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/BitwiseOr.cpp b/tests/validation/NEON/BitwiseOr.cpp
index cef712f626..61d1273b37 100644
--- a/tests/validation/NEON/BitwiseOr.cpp
+++ b/tests/validation/NEON/BitwiseOr.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -53,7 +53,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEBitwiseOrFixture<uint8_t>, framework::Dataset
validate(Accessor(_target), _reference);
}
TEST_SUITE_END() // BitwiseOr
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/BitwiseXor.cpp b/tests/validation/NEON/BitwiseXor.cpp
index 3f973935df..727052ed6b 100644
--- a/tests/validation/NEON/BitwiseXor.cpp
+++ b/tests/validation/NEON/BitwiseXor.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -53,7 +53,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEBitwiseXorFixture<uint8_t>, framework::Datase
validate(Accessor(_target), _reference);
}
TEST_SUITE_END() // BitwiseXor
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/BoundingBoxTransform.cpp b/tests/validation/NEON/BoundingBoxTransform.cpp
index c662c4107c..2ca2434150 100644
--- a/tests/validation/NEON/BoundingBoxTransform.cpp
+++ b/tests/validation/NEON/BoundingBoxTransform.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -153,7 +153,7 @@ TEST_SUITE_END() // QASYMM16
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // BBoxTransform
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Cast.cpp b/tests/validation/NEON/Cast.cpp
index c4c350a536..db73bea9cb 100644
--- a/tests/validation/NEON/Cast.cpp
+++ b/tests/validation/NEON/Cast.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -188,7 +188,7 @@ CAST_SUITE(F32_to_S32, DataType::F32, DataType::S32, NECastToS32Fixture<float>,
CAST_SUITE(F32_to_U8, DataType::F32, DataType::S32, NECastToS32Fixture<float>, CastF32toS32Dataset, one_tolerance)
TEST_SUITE_END() // Cast
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ChannelCombine.cpp b/tests/validation/NEON/ChannelCombine.cpp
index d17f9615e1..924119e5bb 100644
--- a/tests/validation/NEON/ChannelCombine.cpp
+++ b/tests/validation/NEON/ChannelCombine.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -106,7 +106,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEChannelCombineFixture<uint8_t>, framework::Da
TEST_SUITE_END() // YUVPlanar
TEST_SUITE_END() // ChannelCombine
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ChannelExtract.cpp b/tests/validation/NEON/ChannelExtract.cpp
index 559a014e5d..ba639e4f88 100644
--- a/tests/validation/NEON/ChannelExtract.cpp
+++ b/tests/validation/NEON/ChannelExtract.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -99,7 +99,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEChannelExtractFixture<uint8_t>, framework::Da
TEST_SUITE_END() // YUVPlanar
TEST_SUITE_END() // ChannelExtract
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
diff --git a/tests/validation/NEON/ChannelShuffle.cpp b/tests/validation/NEON/ChannelShuffle.cpp
index d0fa82fc53..9a2a9f24f0 100644
--- a/tests/validation/NEON/ChannelShuffle.cpp
+++ b/tests/validation/NEON/ChannelShuffle.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -134,7 +134,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // ChannelShuffle
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ColorConvert.cpp b/tests/validation/NEON/ColorConvert.cpp
index ba4df97907..9e2d5b70b3 100644
--- a/tests/validation/NEON/ColorConvert.cpp
+++ b/tests/validation/NEON/ColorConvert.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -234,7 +234,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEColorConvertFixture<uint8_t>, framework::Data
TEST_SUITE_END() // NVtoYUV
TEST_SUITE_END() // ColorConvert
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ConvertFullyConnectedWeights.cpp b/tests/validation/NEON/ConvertFullyConnectedWeights.cpp
index e0fefe30e3..65dbbcc55b 100644
--- a/tests/validation/NEON/ConvertFullyConnectedWeights.cpp
+++ b/tests/validation/NEON/ConvertFullyConnectedWeights.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -131,7 +131,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEConvertFullyConnectedWeightsFixture<uint8_t>,
TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // ConvertFullyConnectedWeights
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Convolution.cpp b/tests/validation/NEON/Convolution.cpp
index 13bc34c995..2fb43273b1 100644
--- a/tests/validation/NEON/Convolution.cpp
+++ b/tests/validation/NEON/Convolution.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -45,7 +45,7 @@ namespace
{
/** Tolerance value for comparing reference's output against implementation
*
- * This is due to the fact that NEON target performs multiplication with reciprocal of scale,
+ * This is due to the fact that Neon target performs multiplication with reciprocal of scale,
* while reference performs direct division with scale.
*/
constexpr AbsoluteTolerance<uint8_t> tolerance_u8(1);
@@ -289,7 +289,7 @@ TEST_SUITE_END() // S16
TEST_SUITE_END() // Separable9x9
TEST_SUITE_END() // CustomConvolution
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ConvolutionLayer.cpp b/tests/validation/NEON/ConvolutionLayer.cpp
index 9dff36b139..6b152c9b68 100644
--- a/tests/validation/NEON/ConvolutionLayer.cpp
+++ b/tests/validation/NEON/ConvolutionLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -573,7 +573,7 @@ TEST_SUITE_END() // Quantized
TEST_SUITE_END() // DirectGEMMConv2d
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Copy.cpp b/tests/validation/NEON/Copy.cpp
index 7bcb00810f..e2e5210e89 100644
--- a/tests/validation/NEON/Copy.cpp
+++ b/tests/validation/NEON/Copy.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -92,7 +92,7 @@ TEST_SUITE_END() // U16
TEST_SUITE_END() // FixedSeed
TEST_SUITE_END() // Copy
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/CropResize.cpp b/tests/validation/NEON/CropResize.cpp
index 298d393312..df7166bfdc 100644
--- a/tests/validation/NEON/CropResize.cpp
+++ b/tests/validation/NEON/CropResize.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -187,7 +187,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall,
TEST_SUITE_END() // S32
TEST_SUITE_END() // CropResize
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/DeconvolutionLayer.cpp b/tests/validation/NEON/DeconvolutionLayer.cpp
index 734e24fbea..adb5d1709d 100644
--- a/tests/validation/NEON/DeconvolutionLayer.cpp
+++ b/tests/validation/NEON/DeconvolutionLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -386,7 +386,7 @@ TEST_SUITE_END() // QASYMM8_SIGNED
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // DeconvolutionLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/DepthConvertLayer.cpp b/tests/validation/NEON/DepthConvertLayer.cpp
index 8b581a2ce7..60631181bf 100644
--- a/tests/validation/NEON/DepthConvertLayer.cpp
+++ b/tests/validation/NEON/DepthConvertLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -608,7 +608,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEDepthConvertLayerToU8Fixture<int32_t>, framew
TEST_SUITE_END() // S32_to_U8
TEST_SUITE_END() // DepthConvertLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/DepthToSpaceLayer.cpp b/tests/validation/NEON/DepthToSpaceLayer.cpp
index d93437e36c..46ac59e95c 100644
--- a/tests/validation/NEON/DepthToSpaceLayer.cpp
+++ b/tests/validation/NEON/DepthToSpaceLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -109,7 +109,7 @@ TEST_SUITE_END()
TEST_SUITE_END()
TEST_SUITE_END() // DepthToSpace
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/DepthwiseConvolutionLayer.cpp b/tests/validation/NEON/DepthwiseConvolutionLayer.cpp
index b38818d475..7a1a8ae15e 100644
--- a/tests/validation/NEON/DepthwiseConvolutionLayer.cpp
+++ b/tests/validation/NEON/DepthwiseConvolutionLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -832,7 +832,7 @@ TEST_SUITE_END() // QSYMM8_PER_CHANNEL
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // DepthwiseConvLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp b/tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp
index d379ce728e..e1af732400 100644
--- a/tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp
+++ b/tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -172,7 +172,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEDepthwiseConvolutionLayerNativeFixture<float>
TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // DepthwiseConvolutionLayerNative
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
-} // namespace arm_compute \ No newline at end of file
+} // namespace arm_compute
diff --git a/tests/validation/NEON/DequantizationLayer.cpp b/tests/validation/NEON/DequantizationLayer.cpp
index bce60c7891..82a2149152 100644
--- a/tests/validation/NEON/DequantizationLayer.cpp
+++ b/tests/validation/NEON/DequantizationLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -149,7 +149,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEDequantizationLayerFixture<float>, framework:
TEST_SUITE_END() // FP32
TEST_SUITE_END() // DequantizationLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Derivative.cpp b/tests/validation/NEON/Derivative.cpp
index aae41e4f70..b118f2fb88 100644
--- a/tests/validation/NEON/Derivative.cpp
+++ b/tests/validation/NEON/Derivative.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -69,7 +69,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEDerivativeFixture, framework::DatasetMode::NI
}
TEST_SUITE_END() // Derivative
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/DetectionPostProcessLayer.cpp b/tests/validation/NEON/DetectionPostProcessLayer.cpp
index 80b1856e5f..a166402a79 100644
--- a/tests/validation/NEON/DetectionPostProcessLayer.cpp
+++ b/tests/validation/NEON/DetectionPostProcessLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -150,7 +150,7 @@ inline void base_test_case(DetectionPostProcessLayerInfo info, DataType data_typ
quantize_and_fill_tensor(Accessor(anchors), anchors_vector);
}
- // Determine the output through the NEON kernel
+ // Determine the output through the Neon kernel
Tensor output_boxes;
Tensor output_classes;
Tensor output_scores;
@@ -384,7 +384,7 @@ TEST_CASE(Quantized_regular, framework::DatasetMode::ALL)
TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // DetectionPostProcessLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Dilate.cpp b/tests/validation/NEON/Dilate.cpp
index 3c096f7ce6..362e4eb4cd 100644
--- a/tests/validation/NEON/Dilate.cpp
+++ b/tests/validation/NEON/Dilate.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -69,7 +69,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEDilateFixture<uint8_t>, framework::DatasetMod
}
TEST_SUITE_END() // Dilate
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/DilatedConvolutionLayer.cpp b/tests/validation/NEON/DilatedConvolutionLayer.cpp
index cf2f5f2ea4..2f0fce2ce0 100644
--- a/tests/validation/NEON/DilatedConvolutionLayer.cpp
+++ b/tests/validation/NEON/DilatedConvolutionLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -188,7 +188,7 @@ TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // GEMMDilatedConvolutionLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/DirectConvolutionLayer.cpp b/tests/validation/NEON/DirectConvolutionLayer.cpp
index afd9e3952f..6c47fa1cf8 100644
--- a/tests/validation/NEON/DirectConvolutionLayer.cpp
+++ b/tests/validation/NEON/DirectConvolutionLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -293,7 +293,7 @@ FIXTURE_DATA_TEST_CASE(RunLargeUsecase, NEDirectConvolutionLayerFixture<float>,
TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // DirectConvolutionLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseAbsoluteValue.cpp b/tests/validation/NEON/ElementwiseAbsoluteValue.cpp
index f135ba9913..87f4c7f187 100644
--- a/tests/validation/NEON/ElementwiseAbsoluteValue.cpp
+++ b/tests/validation/NEON/ElementwiseAbsoluteValue.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -108,7 +108,7 @@ TEST_SUITE_END() // S32
TEST_SUITE_END() // Integer
TEST_SUITE_END() // AbsLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseDivision.cpp b/tests/validation/NEON/ElementwiseDivision.cpp
index 120bca032b..3656560281 100644
--- a/tests/validation/NEON/ElementwiseDivision.cpp
+++ b/tests/validation/NEON/ElementwiseDivision.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -43,7 +43,7 @@ namespace validation
namespace
{
RelativeTolerance<float> tolerance_fp32(0.000001f);
-AbsoluteTolerance<int> tolerance_zero_s32(1); // Tolerance for S32 division
+AbsoluteTolerance<int> tolerance_zero_s32(1); // Tolerance for S32 division
/** Input data sets **/
const auto ElementwiseDivisionS32Dataset = combine(combine(framework::dataset::make("DataType", DataType::S32),
@@ -134,7 +134,7 @@ TEST_SUITE_END() // S32
TEST_SUITE_END() // Integer
TEST_SUITE_END() // ElementwiseDivision
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseExpLayer.cpp b/tests/validation/NEON/ElementwiseExpLayer.cpp
index 3168b9ffe2..211e10fa45 100644
--- a/tests/validation/NEON/ElementwiseExpLayer.cpp
+++ b/tests/validation/NEON/ElementwiseExpLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -83,7 +83,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // ExpLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseLog.cpp b/tests/validation/NEON/ElementwiseLog.cpp
index 81e6dc87e8..3115ed6065 100644
--- a/tests/validation/NEON/ElementwiseLog.cpp
+++ b/tests/validation/NEON/ElementwiseLog.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -89,7 +89,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NELogLayerFixture<float>, framework::DatasetMod
TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // LogLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseMax.cpp b/tests/validation/NEON/ElementwiseMax.cpp
index 449d5db3fc..4bc263184e 100644
--- a/tests/validation/NEON/ElementwiseMax.cpp
+++ b/tests/validation/NEON/ElementwiseMax.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -200,7 +200,7 @@ TEST_SUITE_END() // F32
TEST_SUITE_END() // Float
TEST_SUITE_END() // ElementwiseMax
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseMin.cpp b/tests/validation/NEON/ElementwiseMin.cpp
index 6678a1b52d..3836b90308 100644
--- a/tests/validation/NEON/ElementwiseMin.cpp
+++ b/tests/validation/NEON/ElementwiseMin.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -202,7 +202,7 @@ TEST_SUITE_END() // F32
TEST_SUITE_END() // Float
TEST_SUITE_END() // ElementwiseMin
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseNegation.cpp b/tests/validation/NEON/ElementwiseNegation.cpp
index ae7dca1ef0..629baa80e6 100644
--- a/tests/validation/NEON/ElementwiseNegation.cpp
+++ b/tests/validation/NEON/ElementwiseNegation.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -114,7 +114,7 @@ TEST_SUITE_END() // S32
TEST_SUITE_END() // Integer
TEST_SUITE_END() // NegLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwisePower.cpp b/tests/validation/NEON/ElementwisePower.cpp
index beef1c874b..4305387c5f 100644
--- a/tests/validation/NEON/ElementwisePower.cpp
+++ b/tests/validation/NEON/ElementwisePower.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -133,7 +133,7 @@ TEST_SUITE_END() // F32
TEST_SUITE_END() // Float
TEST_SUITE_END() // ElementwisePower
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseRound.cpp b/tests/validation/NEON/ElementwiseRound.cpp
index e0f24128f6..5ff81a5d8a 100644
--- a/tests/validation/NEON/ElementwiseRound.cpp
+++ b/tests/validation/NEON/ElementwiseRound.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -82,7 +82,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NERoundLayerFixture<float>, framework::DatasetM
TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // RoundLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseRsqrtLayer.cpp b/tests/validation/NEON/ElementwiseRsqrtLayer.cpp
index 58efa28b31..f41500cc0b 100644
--- a/tests/validation/NEON/ElementwiseRsqrtLayer.cpp
+++ b/tests/validation/NEON/ElementwiseRsqrtLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -84,7 +84,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // RsqrtLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseSin.cpp b/tests/validation/NEON/ElementwiseSin.cpp
index a2e6cb3760..9b212e264f 100644
--- a/tests/validation/NEON/ElementwiseSin.cpp
+++ b/tests/validation/NEON/ElementwiseSin.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -90,7 +90,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // SinLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ElementwiseSquareDiff.cpp b/tests/validation/NEON/ElementwiseSquareDiff.cpp
index b50db3d4a3..069cbbd7fa 100644
--- a/tests/validation/NEON/ElementwiseSquareDiff.cpp
+++ b/tests/validation/NEON/ElementwiseSquareDiff.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -205,7 +205,7 @@ TEST_SUITE_END() // F32
TEST_SUITE_END() // Float
TEST_SUITE_END() // ElementwiseSquaredDiff
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/FFT.cpp b/tests/validation/NEON/FFT.cpp
index bc528dd9a6..7125158a21 100644
--- a/tests/validation/NEON/FFT.cpp
+++ b/tests/validation/NEON/FFT.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -173,7 +173,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // FFTConvolutionLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Fill.cpp b/tests/validation/NEON/Fill.cpp
index 5fe92ca35e..0073f22677 100644
--- a/tests/validation/NEON/Fill.cpp
+++ b/tests/validation/NEON/Fill.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -100,7 +100,6 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEFillFixture<uint32_t>, framework::DatasetMode
}
TEST_SUITE_END() // U32
-
TEST_SUITE(S32)
FIXTURE_DATA_TEST_CASE(RunSmall, NEFillFixture<int32_t>, framework::DatasetMode::ALL, combine(datasets::SmallShapes(), framework::dataset::make("DataType", DataType::S32)))
{
@@ -118,7 +117,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEFillFixture<float>, framework::DatasetMode::A
TEST_SUITE_END() // F32
TEST_SUITE_END() // Fill
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Flatten.cpp b/tests/validation/NEON/Flatten.cpp
index daadd56a6c..4ebd897c7a 100644
--- a/tests/validation/NEON/Flatten.cpp
+++ b/tests/validation/NEON/Flatten.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -100,7 +100,7 @@ TEST_SUITE_END() // FP16
TEST_SUITE_END() // Float
TEST_SUITE_END() // FlattenLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/FuseBatchNormalization.cpp b/tests/validation/NEON/FuseBatchNormalization.cpp
index 9fc3353aaf..62265c6ac9 100644
--- a/tests/validation/NEON/FuseBatchNormalization.cpp
+++ b/tests/validation/NEON/FuseBatchNormalization.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -214,7 +214,7 @@ TEST_SUITE_END() // FP16
TEST_SUITE_END() // Float
TEST_SUITE_END() // DepthwiseConvolution
TEST_SUITE_END() // FuseBatchNormalization
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
-} // namespace arm_compute \ No newline at end of file
+} // namespace arm_compute
diff --git a/tests/validation/NEON/GEMMLowp.cpp b/tests/validation/NEON/GEMMLowp.cpp
index 178e7c9388..518f4804a0 100644
--- a/tests/validation/NEON/GEMMLowp.cpp
+++ b/tests/validation/NEON/GEMMLowp.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -547,7 +547,7 @@ TEST_SUITE_END() // BoundedReLu
TEST_SUITE_END() // QuantizeDownInt32ToInt16ScaleByFixedPoint
TEST_SUITE_END() // OutputStage
TEST_SUITE_END() // GEMMLowp
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Gather.cpp b/tests/validation/NEON/Gather.cpp
index d2d5df802a..ca1e166bd1 100644
--- a/tests/validation/NEON/Gather.cpp
+++ b/tests/validation/NEON/Gather.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -183,7 +183,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge,
TEST_SUITE_END() // U16
TEST_SUITE_END() // Gather
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/GenerateProposalsLayer.cpp b/tests/validation/NEON/GenerateProposalsLayer.cpp
index 6a28fecf7f..960c2054e7 100644
--- a/tests/validation/NEON/GenerateProposalsLayer.cpp
+++ b/tests/validation/NEON/GenerateProposalsLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -415,7 +415,7 @@ TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // GenerateProposals
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/HOGDetector.cpp b/tests/validation/NEON/HOGDetector.cpp
index dd138d75e3..5da80e23bb 100644
--- a/tests/validation/NEON/HOGDetector.cpp
+++ b/tests/validation/NEON/HOGDetector.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -43,7 +43,7 @@ namespace validation
namespace
{
/* Set the tolerance (percentage) used when validating the score of detection window.
- Note: High tolerance is required due to divergence between CL and NEON detection window scores. */
+ Note: High tolerance is required due to divergence between CL and Neon detection window scores. */
RelativeTolerance<float> tolerance(1.0f);
/* Input dataset (values must be a multiple of the HOGInfo block_size) */
diff --git a/tests/validation/NEON/Im2Col.cpp b/tests/validation/NEON/Im2Col.cpp
index 7270744fcb..156957a601 100644
--- a/tests/validation/NEON/Im2Col.cpp
+++ b/tests/validation/NEON/Im2Col.cpp
@@ -205,7 +205,7 @@ TEST_CASE(PaddedChannelNHWC, framework::DatasetMode::PRECOMMIT)
}
TEST_SUITE_END() // Special Cases
TEST_SUITE_END() // Im2Col
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/InstanceNormalizationLayer.cpp b/tests/validation/NEON/InstanceNormalizationLayer.cpp
index 1073a7f6f7..593ef0ad99 100644
--- a/tests/validation/NEON/InstanceNormalizationLayer.cpp
+++ b/tests/validation/NEON/InstanceNormalizationLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -123,7 +123,7 @@ TEST_SUITE_END() // FP16
#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
TEST_SUITE_END() // InstanceNormalizationLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/L2NormalizeLayer.cpp b/tests/validation/NEON/L2NormalizeLayer.cpp
index 82e4beb05a..56223c44d5 100644
--- a/tests/validation/NEON/L2NormalizeLayer.cpp
+++ b/tests/validation/NEON/L2NormalizeLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -139,7 +139,7 @@ TEST_SUITE_END() // FP16
#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
TEST_SUITE_END() // L2NormalizeLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/LSTMLayer.cpp b/tests/validation/NEON/LSTMLayer.cpp
index 0850dc6954..c4645563bf 100644
--- a/tests/validation/NEON/LSTMLayer.cpp
+++ b/tests/validation/NEON/LSTMLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -181,7 +181,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NELSTMLayerFixture<half>, framework::DatasetMod
TEST_SUITE_END() // FP16
#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
TEST_SUITE_END() // LSTMLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/LSTMLayerQuantized.cpp b/tests/validation/NEON/LSTMLayerQuantized.cpp
index fbcece8ffc..d391267e3e 100644
--- a/tests/validation/NEON/LSTMLayerQuantized.cpp
+++ b/tests/validation/NEON/LSTMLayerQuantized.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -602,7 +602,7 @@ TEST_SUITE_END() // IntegrationTestCase
// *INDENT-ON*
TEST_SUITE_END() // LSTMLayerQuantized
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Logical.cpp b/tests/validation/NEON/Logical.cpp
index 6f1c55b33c..271d22f877 100644
--- a/tests/validation/NEON/Logical.cpp
+++ b/tests/validation/NEON/Logical.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -85,7 +85,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NELogicalNotFixture<uint8_t>, framework::Datase
validate(Accessor(_target), _reference);
}
TEST_SUITE_END() // LogicalNot
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
-} // namespace arm_compute \ No newline at end of file
+} // namespace arm_compute
diff --git a/tests/validation/NEON/MaxUnpoolingLayer.cpp b/tests/validation/NEON/MaxUnpoolingLayer.cpp
index a33ec2885e..27f131fa51 100644
--- a/tests/validation/NEON/MaxUnpoolingLayer.cpp
+++ b/tests/validation/NEON/MaxUnpoolingLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -76,7 +76,7 @@ TEST_SUITE_END() // FP16
#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
TEST_SUITE_END() // Float
TEST_SUITE_END() // PoolingLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/MeanStdDevNormalizationLayer.cpp b/tests/validation/NEON/MeanStdDevNormalizationLayer.cpp
index 11f97a5e84..20e3bd5325 100644
--- a/tests/validation/NEON/MeanStdDevNormalizationLayer.cpp
+++ b/tests/validation/NEON/MeanStdDevNormalizationLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -118,7 +118,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // MeanStdNormalizationLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/MinMaxLocation.cpp b/tests/validation/NEON/MinMaxLocation.cpp
index 2f9cd3dc77..581dcb1fe2 100644
--- a/tests/validation/NEON/MinMaxLocation.cpp
+++ b/tests/validation/NEON/MinMaxLocation.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -92,7 +92,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEMinMaxLocationFixture<float>, framework::Data
TEST_SUITE_END() // F32
TEST_SUITE_END() // MinMaxLocation
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/NormalizationLayer.cpp b/tests/validation/NEON/NormalizationLayer.cpp
index d910cbdc45..7260d1044e 100644
--- a/tests/validation/NEON/NormalizationLayer.cpp
+++ b/tests/validation/NEON/NormalizationLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -126,7 +126,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // NormalizationLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/PReluLayer.cpp b/tests/validation/NEON/PReluLayer.cpp
index c4b3c88787..69a05175ad 100644
--- a/tests/validation/NEON/PReluLayer.cpp
+++ b/tests/validation/NEON/PReluLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -206,7 +206,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // PReluLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/PadLayer.cpp b/tests/validation/NEON/PadLayer.cpp
index ea9ef72e13..4947af3423 100644
--- a/tests/validation/NEON/PadLayer.cpp
+++ b/tests/validation/NEON/PadLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -188,7 +188,7 @@ TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // PadLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/PoolingLayer.cpp b/tests/validation/NEON/PoolingLayer.cpp
index cc5452b122..24e552ed0c 100644
--- a/tests/validation/NEON/PoolingLayer.cpp
+++ b/tests/validation/NEON/PoolingLayer.cpp
@@ -246,7 +246,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEPoolingLayerQuantizedFixture<int8_t>, framewo
TEST_SUITE_END() // QASYMM8_SIGNED
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // PoolingLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/PriorBoxLayer.cpp b/tests/validation/NEON/PriorBoxLayer.cpp
index cc63877a5f..9a9b9a8e3d 100644
--- a/tests/validation/NEON/PriorBoxLayer.cpp
+++ b/tests/validation/NEON/PriorBoxLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -90,7 +90,7 @@ TEST_SUITE_END() // Float
TEST_SUITE_END() // FP32
TEST_SUITE_END() // PriorBoxLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/QLSTMLayerNormalization.cpp b/tests/validation/NEON/QLSTMLayerNormalization.cpp
index 8925d0b39e..617f64ce1d 100644
--- a/tests/validation/NEON/QLSTMLayerNormalization.cpp
+++ b/tests/validation/NEON/QLSTMLayerNormalization.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2020-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -167,7 +167,7 @@ TEST_SUITE(Quantized)
TEST_SUITE(QSYMM16)
/** Tests will be targetting
- * - Comparison between NEON kernel and the exact same but scalar version of reference kernel
+ * - Comparison between Neon kernel and the exact same but scalar version of reference kernel
* - Input shapes of 1D and 2D with the first dimension covers boundary values of 128-bit vector size (0~3 iterations)
* - Weight and bias 1D shape that have same size as that of input shapes
* - Quantization scale is greater and smaller than one.
@@ -179,7 +179,7 @@ TEST_SUITE(QSYMM16)
* - The algorithm has been sensitive to quantization scale but it is hard to fully test
* the sensitivity due to aforementioned reason.
* - Again, it is hard to fully test corner values due to the exact same algorithm of the
- * reference kernel and the NEON kernel.
+ * reference kernel and the Neon kernel.
*/
constexpr uint32_t qsymm16_per_vector = vector_size_byte / sizeof(int16_t);
@@ -216,7 +216,7 @@ FIXTURE_DATA_TEST_CASE(RandomValue2D, NEQLSTMLayerNormalizationFixture<int16_t>,
TEST_SUITE_END() // QSYMM16
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // QLSTMLayerNormalization
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
diff --git a/tests/validation/NEON/QuantizationLayer.cpp b/tests/validation/NEON/QuantizationLayer.cpp
index 36f2937cad..aeee54c835 100644
--- a/tests/validation/NEON/QuantizationLayer.cpp
+++ b/tests/validation/NEON/QuantizationLayer.cpp
@@ -229,7 +229,7 @@ TEST_SUITE_END() // QASYMM8_SIGNED
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // QuantizationLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/RNNLayer.cpp b/tests/validation/NEON/RNNLayer.cpp
index 21e2052713..14d9a5d14e 100644
--- a/tests/validation/NEON/RNNLayer.cpp
+++ b/tests/validation/NEON/RNNLayer.cpp
@@ -144,7 +144,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NERNNLayerFixture<half>, framework::DatasetMode
TEST_SUITE_END() // FP16
#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
TEST_SUITE_END() // RNNLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ROIAlignLayer.cpp b/tests/validation/NEON/ROIAlignLayer.cpp
index e475c46c7d..7bfdddf10d 100644
--- a/tests/validation/NEON/ROIAlignLayer.cpp
+++ b/tests/validation/NEON/ROIAlignLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -160,7 +160,7 @@ TEST_SUITE_END() // QASYMM8_SIGNED
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // RoiAlign
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Range.cpp b/tests/validation/NEON/Range.cpp
index 57e891d09b..fda7b2c448 100644
--- a/tests/validation/NEON/Range.cpp
+++ b/tests/validation/NEON/Range.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -172,7 +172,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // Range
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ReduceMean.cpp b/tests/validation/NEON/ReduceMean.cpp
index d5018927c8..b4a3f0d399 100644
--- a/tests/validation/NEON/ReduceMean.cpp
+++ b/tests/validation/NEON/ReduceMean.cpp
@@ -208,7 +208,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge,
TEST_SUITE_END() // QASYMM8_SIGNED
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // ReduceMean
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ReductionOperation.cpp b/tests/validation/NEON/ReductionOperation.cpp
index ed17e6968e..48c3a1a788 100644
--- a/tests/validation/NEON/ReductionOperation.cpp
+++ b/tests/validation/NEON/ReductionOperation.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -194,7 +194,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEReductionOperationQuantizedFixture<int8_t>, f
TEST_SUITE_END() // QASYMM8_SIGNED
TEST_SUITE_END() // ReductionOperation
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/ReorgLayer.cpp b/tests/validation/NEON/ReorgLayer.cpp
index cd8c10bd61..38bef51ed3 100644
--- a/tests/validation/NEON/ReorgLayer.cpp
+++ b/tests/validation/NEON/ReorgLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -126,7 +126,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEReorgLayerFixture<int8_t>, framework::Dataset
TEST_SUITE_END() // S8
TEST_SUITE_END() // ReorgLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Reverse.cpp b/tests/validation/NEON/Reverse.cpp
index 4278f35b30..3dc3eeee80 100644
--- a/tests/validation/NEON/Reverse.cpp
+++ b/tests/validation/NEON/Reverse.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -156,7 +156,7 @@ TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // Reverse
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Scale.cpp b/tests/validation/NEON/Scale.cpp
index 9a1e9b01b3..bb1ab936d1 100644
--- a/tests/validation/NEON/Scale.cpp
+++ b/tests/validation/NEON/Scale.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -460,7 +460,7 @@ TEST_SUITE_END() // QASYMM8_SIGNED
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // Scale
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Select.cpp b/tests/validation/NEON/Select.cpp
index 199b520ac8..40744581b0 100644
--- a/tests/validation/NEON/Select.cpp
+++ b/tests/validation/NEON/Select.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -140,7 +140,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // Select
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Slice.cpp b/tests/validation/NEON/Slice.cpp
index 54b0fbf9d2..d5549c8cdb 100644
--- a/tests/validation/NEON/Slice.cpp
+++ b/tests/validation/NEON/Slice.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -111,7 +111,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // Slice
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/SpaceToBatchLayer.cpp b/tests/validation/NEON/SpaceToBatchLayer.cpp
index d9fea97e23..61642c6ff9 100644
--- a/tests/validation/NEON/SpaceToBatchLayer.cpp
+++ b/tests/validation/NEON/SpaceToBatchLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -162,7 +162,7 @@ FIXTURE_DATA_TEST_CASE(Large, NESpaceToBatchLayerQuantizedFixture<uint8_t>, fram
TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // SpaceToBatch
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/SpaceToDepthLayer.cpp b/tests/validation/NEON/SpaceToDepthLayer.cpp
index 2cdfb06680..6d87bc4fd4 100644
--- a/tests/validation/NEON/SpaceToDepthLayer.cpp
+++ b/tests/validation/NEON/SpaceToDepthLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -107,7 +107,7 @@ TEST_SUITE_END() // FP16
TEST_SUITE_END() // Float
TEST_SUITE_END() // SpaceToDepthLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Split.cpp b/tests/validation/NEON/Split.cpp
index e7133fa530..72df2ad663 100644
--- a/tests/validation/NEON/Split.cpp
+++ b/tests/validation/NEON/Split.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -166,7 +166,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // Split
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/StackLayer.cpp b/tests/validation/NEON/StackLayer.cpp
index df0de81b4f..d88f713ccd 100644
--- a/tests/validation/NEON/StackLayer.cpp
+++ b/tests/validation/NEON/StackLayer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -366,7 +366,7 @@ FIXTURE_DATA_TEST_CASE(RunLarge, NEStackLayerFixture<char>, framework::DatasetMo
TEST_SUITE_END() // S8
TEST_SUITE_END() // Shapes4D
TEST_SUITE_END() // StackLayer
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/StridedSlice.cpp b/tests/validation/NEON/StridedSlice.cpp
index 8332134b1b..a1b3cef801 100644
--- a/tests/validation/NEON/StridedSlice.cpp
+++ b/tests/validation/NEON/StridedSlice.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -113,7 +113,7 @@ TEST_SUITE_END() // FP32
TEST_SUITE_END() // Float
TEST_SUITE_END() // StridedSlice
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
diff --git a/tests/validation/NEON/Tile.cpp b/tests/validation/NEON/Tile.cpp
index aa96c95aca..2246c491f2 100644
--- a/tests/validation/NEON/Tile.cpp
+++ b/tests/validation/NEON/Tile.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -134,7 +134,7 @@ TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // Quantized
TEST_SUITE_END() // Tile
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/UNIT/DynamicTensor.cpp b/tests/validation/NEON/UNIT/DynamicTensor.cpp
index 464633e7aa..373cc574c8 100644
--- a/tests/validation/NEON/UNIT/DynamicTensor.cpp
+++ b/tests/validation/NEON/UNIT/DynamicTensor.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +117,7 @@ FIXTURE_DATA_TEST_CASE(DynamicTensorType2Pipeline, NEDynamicTensorType2PipelineF
}
TEST_SUITE_END() // DynamicTensor
TEST_SUITE_END() // UNIT
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/UNIT/RuntimeContext.cpp b/tests/validation/NEON/UNIT/RuntimeContext.cpp
index 6070a88d6b..f64d380423 100644
--- a/tests/validation/NEON/UNIT/RuntimeContext.cpp
+++ b/tests/validation/NEON/UNIT/RuntimeContext.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited.
+ * Copyright (c) 2019-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -159,7 +159,7 @@ TEST_CASE(MultipleThreadedScheduller, framework::DatasetMode::ALL)
TEST_SUITE_END() // RuntimeContext
TEST_SUITE_END() // UNIT
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/NEON/Unstack.cpp b/tests/validation/NEON/Unstack.cpp
index aa8dcc5a65..3e8f1ff324 100644
--- a/tests/validation/NEON/Unstack.cpp
+++ b/tests/validation/NEON/Unstack.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited.
+ * Copyright (c) 2018-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -122,7 +122,7 @@ FIXTURE_DATA_TEST_CASE(RunSmall, NEUnstackFixture<uint8_t>, framework::DatasetMo
TEST_SUITE_END() // QASYMM8
TEST_SUITE_END() // Unstack
-TEST_SUITE_END() // NEON
+TEST_SUITE_END() // Neon
} // namespace validation
} // namespace test
} // namespace arm_compute
diff --git a/tests/validation/fixtures/DepthConvertLayerFixture.h b/tests/validation/fixtures/DepthConvertLayerFixture.h
index fa9e6a71b8..937a1a06a9 100644
--- a/tests/validation/fixtures/DepthConvertLayerFixture.h
+++ b/tests/validation/fixtures/DepthConvertLayerFixture.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -67,8 +67,8 @@ protected:
}
else
{
- // When converting S32 to F16, both reference and NEON implementations are + or - infinity outside the F16 range.
- if(dt_in==DataType::S32 && dt_out==DataType::F16)
+ // When converting S32 to F16, both reference and Neon implementations are + or - infinity outside the F16 range.
+ if(dt_in == DataType::S32 && dt_out == DataType::F16)
{
std::uniform_int_distribution<int32_t> distribution_s32(-65504, 65504);
library->fill(tensor, distribution_s32, i);
diff --git a/tests/validation/reference/UtilsQuantizedAsymm.h b/tests/validation/reference/UtilsQuantizedAsymm.h
index 91d0abfb1f..25873acc93 100644
--- a/tests/validation/reference/UtilsQuantizedAsymm.h
+++ b/tests/validation/reference/UtilsQuantizedAsymm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,7 @@ inline int32_t asymm_rounding_divide_by_pow2(int32_t x, int exponent)
return (x >> exponent) + ((x & mask) > threshold ? 1 : 0);
}
-/** Multiplication of two integers. The same as ARMv7 NEON VQRDMULH instruction. */
+/** Multiplication of two integers. The same as ARMv7 Neon VQRDMULH instruction. */
inline int32_t asymm_int_mult(int32_t a, int32_t b)
{
bool overflow = a == b && a == std::numeric_limits<int32_t>::min();
diff --git a/utils/CommonGraphOptions.h b/utils/CommonGraphOptions.h
index 13cd653e46..98f020d79e 100644
--- a/utils/CommonGraphOptions.h
+++ b/utils/CommonGraphOptions.h
@@ -40,7 +40,7 @@ namespace utils
*
* --help : Print the example's help message.
* --threads : The number of threads to be used by the example during execution.
- * --target : Execution target to be used by the examples. Supported target options: NEON, CL, GC.
+ * --target : Execution target to be used by the examples. Supported target options: Neon, CL, GC.
* --type : Data type to be used by the examples. Supported data type options: QASYMM8, F16, F32.
* --layout : Data layout to be used by the examples. Supported data layout options : NCHW, NHWC.
* --enable-tuner : Toggle option to enable the OpenCL dynamic tuner.
diff --git a/utils/GraphUtils.h b/utils/GraphUtils.h
index acd924da28..056648451b 100644
--- a/utils/GraphUtils.h
+++ b/utils/GraphUtils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited.
+ * Copyright (c) 2017-2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -673,7 +673,7 @@ inline TensorShape permute_shape(TensorShape tensor_shape, DataLayout in_data_la
/** Utility function to return the TargetHint
*
- * @param[in] target Integer value which expresses the selected target. Must be 0 for NEON or 1 for OpenCL or 2 (OpenCL with Tuner)
+ * @param[in] target Integer value which expresses the selected target. Must be 0 for Neon or 1 for OpenCL or 2 (OpenCL with Tuner)
*
* @return the TargetHint
*/