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authorViet-Hoa Do <viet-hoa.do@arm.com>2022-09-13 10:20:06 +0100
committerViet-Hoa Do <viet-hoa.do@arm.com>2022-09-16 12:50:18 +0000
commit622b8ad4648af55a6743d38105725958b0075020 (patch)
tree013ba06a5f13593b865ea923f9ae6225d4c13445
parentc4f2743951473f8d97f5a43767fdbb31a4df967c (diff)
downloadComputeLibrary-622b8ad4648af55a6743d38105725958b0075020.tar.gz
Fix bug in QASYMM8_SIGNED to F32 cast layer
Resolves: COMPMID-5580 Signed-off-by: Viet-Hoa Do <viet-hoa.do@arm.com> Change-Id: Ia731560c23a6ab2e0ead5a857fbabb9cbc25154c Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/VisualCompute/ComputeLibrary/+/452428 Tested-by: bsgcomp <bsgcomp@arm.com> Reviewed-by: Pablo Tello <pablo.tello@arm.com> Comments-Addressed: bsgcomp <bsgcomp@arm.com> Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8268 Comments-Addressed: Arm Jenkins <bsgcomp@arm.com> Benchmark: Arm Jenkins <bsgcomp@arm.com> Tested-by: Arm Jenkins <bsgcomp@arm.com> Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
-rw-r--r--src/cpu/kernels/CpuCastKernel.cpp2
-rw-r--r--tests/datasets/ShapeDatasets.h6
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/kernels/CpuCastKernel.cpp b/src/cpu/kernels/CpuCastKernel.cpp
index e1314e61da..15a9ddcab4 100644
--- a/src/cpu/kernels/CpuCastKernel.cpp
+++ b/src/cpu/kernels/CpuCastKernel.cpp
@@ -288,7 +288,7 @@ void CpuCastKernel::run_op(ITensorPack &tensors, const Window &window, const Thr
int x = window_start_x;
for(; x <= (window_end_x - window_step_x); x += window_step_x)
{
- const int8x16_t texels_s8 = vld1q_s8(reinterpret_cast<int8_t *>(src.ptr()));
+ const int8x16_t texels_s8 = vld1q_s8(src_ptr + x);
const int16x8x2_t texels =
{
diff --git a/tests/datasets/ShapeDatasets.h b/tests/datasets/ShapeDatasets.h
index 31c9b9e051..f0ad9fa693 100644
--- a/tests/datasets/ShapeDatasets.h
+++ b/tests/datasets/ShapeDatasets.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021 Arm Limited.
+ * Copyright (c) 2017-2022 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -203,8 +203,8 @@ public:
TensorShape{ 1U, 16U },
TensorShape{ 27U, 13U, 7U },
TensorShape{ 7U, 7U, 17U, 2U },
- // Batch size 4
- TensorShape{ 27U, 13U, 2U, 4U },
+ // Batch size 4 and 2 SIMD iterations
+ TensorShape{ 33U, 13U, 2U, 4U },
// Arbitrary batch size
TensorShape{ 11U, 11U, 3U, 5U }
})