From 31ae9f09bb3535975595e999fbc7baca889e46e8 Mon Sep 17 00:00:00 2001 From: alexander Date: Thu, 10 Feb 2022 16:15:54 +0000 Subject: MLECO-2682: CMake and source refactoring. MLECO-2930: logging macros were extracted from hal.h and used separately around the code. MLECO-2931: arm_math lib introduced, cmsis-dsp removed from top level linkage. MLECO-2915: platform related post-build steps. Change-Id: Id718884e22f262a5c070ded3f3f5d4b048820147 Signed-off-by: alexander --- .../mps3/cmake/templates/mem_regions.h.template | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 source/hal/platform/mps3/cmake/templates/mem_regions.h.template (limited to 'source/hal/platform/mps3/cmake/templates/mem_regions.h.template') diff --git a/source/hal/platform/mps3/cmake/templates/mem_regions.h.template b/source/hal/platform/mps3/cmake/templates/mem_regions.h.template new file mode 100644 index 0000000..72978ce --- /dev/null +++ b/source/hal/platform/mps3/cmake/templates/mem_regions.h.template @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef MEM_REGION_DEFS_H +#define MEM_REGION_DEFS_H + +#cmakedefine ITCM_SIZE (@ITCM_SIZE@) /* ITCM size */ +#cmakedefine DTCM_BLK_SIZE (@DTCM_BLK_SIZE@) /* DTCM size, 4 banks of this size available */ +#cmakedefine BRAM_SIZE (@BRAM_SIZE@) /* BRAM size */ +#cmakedefine ISRAM0_SIZE (@ISRAM0_SIZE@) /* ISRAM0 size */ +#cmakedefine ISRAM1_SIZE (@ISRAM1_SIZE@) /* ISRAM1 size */ +#cmakedefine QSPI_SRAM_SIZE (@QSPI_SRAM_SIZE@) /* QSPI Flash size */ +#cmakedefine DDR4_BLK_SIZE (@DDR4_BLK_SIZE@) /* DDR4 block size */ + +#cmakedefine ITCM_BASE_NS (@ITCM_BASE_NS@) /* Instruction TCM Non-Secure base address */ +#cmakedefine BRAM_BASE_NS (@BRAM_BASE_NS@) /* CODE SRAM Non-Secure base address */ +#cmakedefine DTCM0_BASE_NS (@DTCM0_BASE_NS@) /* Data TCM block 0 Non-Secure base address */ +#cmakedefine DTCM1_BASE_NS (@DTCM1_BASE_NS@) /* Data TCM block 1 Non-Secure base address */ +#cmakedefine DTCM2_BASE_NS (@DTCM2_BASE_NS@) /* Data TCM block 2 Non-Secure base address */ +#cmakedefine DTCM3_BASE_NS (@DTCM3_BASE_NS@) /* Data TCM block 3 Non-Secure base address */ +#cmakedefine ISRAM0_BASE_NS (@ISRAM0_BASE_NS@) /* Internal SRAM Area Non-Secure base address */ +#cmakedefine ISRAM1_BASE_NS (@ISRAM1_BASE_NS@) /* Internal SRAM Area Non-Secure base address */ +#cmakedefine QSPI_SRAM_BASE_NS (@QSPI_SRAM_BASE_NS@) /* QSPI SRAM Non-Secure base address */ +#cmakedefine DDR4_BLK0_BASE_NS (@DDR4_BLK0_BASE_NS@) /* DDR4 block 0 Non-Secure base address */ +#cmakedefine DDR4_BLK1_BASE_NS (@DDR4_BLK1_BASE_NS@) /* DDR4 block 1 Non-Secure base address */ +#cmakedefine DDR4_BLK2_BASE_NS (@DDR4_BLK2_BASE_NS@) /* DDR4 block 2 Non-Secure base address */ +#cmakedefine DDR4_BLK3_BASE_NS (@DDR4_BLK3_BASE_NS@) /* DDR4 block 3 Non-Secure base address */ + +#cmakedefine ITCM_BASE_S (@ITCM_BASE_S@) /* Instruction TCM Secure base address */ +#cmakedefine BRAM_BASE_S (@BRAM_BASE_S@) /* CODE SRAM Secure base address */ +#cmakedefine DTCM0_BASE_S (@DTCM0_BASE_S@) /* Data TCM block 0 Secure base address */ +#cmakedefine DTCM1_BASE_S (@DTCM1_BASE_S@) /* Data TCM block 1 Secure base address */ +#cmakedefine DTCM2_BASE_S (@DTCM2_BASE_S@) /* Data TCM block 2 Secure base address */ +#cmakedefine DTCM3_BASE_S (@DTCM3_BASE_S@) /* Data TCM block 3 Secure base address */ +#cmakedefine ISRAM0_BASE_S (@ISRAM0_BASE_S@) /* Internal SRAM Area Secure base address */ +#cmakedefine ISRAM1_BASE_S (@ISRAM1_BASE_S@) /* Internal SRAM Area Secure base address */ +#cmakedefine DDR4_BLK0_BASE_S (@DDR4_BLK0_BASE_S@) /* DDR4 block 0 Secure base address */ +#cmakedefine DDR4_BLK1_BASE_S (@DDR4_BLK1_BASE_S@) /* DDR4 block 1 Secure base address */ +#cmakedefine DDR4_BLK2_BASE_S (@DDR4_BLK2_BASE_S@) /* DDR4 block 2 Secure base address */ +#cmakedefine DDR4_BLK3_BASE_S (@DDR4_BLK3_BASE_S@) /* DDR4 block 3 Secure base address */ + +#endif /* MEM_REGION_DEFS_H */ -- cgit v1.2.1