From c5d8bda3c6f743ec2725bf281874d4b6431122c3 Mon Sep 17 00:00:00 2001 From: Isabella Gottardi Date: Wed, 21 Jul 2021 10:35:08 +0100 Subject: MLECO-1982: Update to using latest ethos-u embedded components Change-Id: I744a4eb2553207004c9403b956e5bd9e9b352bfb Signed-off-by: Isabella Gottardi --- .../bare-metal/bsp/bsp-packs/mps3/uart_stdout.c | 4 +++ .../bsp/bsp-packs/simple_platform/uart_pl011.c | 8 +++-- .../platforms/bare-metal/timer/baremetal_timer.c | 41 ++++++++++------------ 3 files changed, 29 insertions(+), 24 deletions(-) (limited to 'source/application/hal/platforms/bare-metal') diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c index ed12c8b..3211c4d 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c +++ b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c @@ -111,6 +111,10 @@ bool GetLine(char *lp, unsigned int len) lp++; /* Increment line pointer */ cnt++; /* and count. */ c = LF; + UartPutc (*lp = c); /* Echo and store character. */ + fflush (stdout); + lp++; /* Increment line pointer */ + cnt++; /* and count. */ break; default: UartPutc (*lp = c); /* Echo and store character. */ diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/uart_pl011.c b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/uart_pl011.c index b2dee14..1cbf70c 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/uart_pl011.c +++ b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/uart_pl011.c @@ -199,11 +199,15 @@ bool GetLine (char *lp, unsigned int len) case 0: *lp = 0; /* ESC - stop editing line. */ return false; - case CR: /* CR - done, stop editing line. */ + case CR: /* CR - done, stop editing line. */ + UartPutc (*lp = c); /* Echo and store character. */ + lp++; /* Increment line pointer */ + cnt++; /* and count. */ + c = LF; UartPutc (*lp = c); /* Echo and store character. */ + fflush (stdout); lp++; /* Increment line pointer */ cnt++; /* and count. */ - c = LF; break; default: UartPutc (*lp = c); /* echo and store character. */ diff --git a/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c b/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c index 00028bd..c8e7252 100644 --- a/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c +++ b/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c @@ -25,6 +25,8 @@ #include "pmu_ethosu.h" +extern struct ethosu_driver ethosu_drv; /* Default Ethos-U55 device driver */ + /** * @brief Initialises the PMU and enables the cycle counter. **/ @@ -183,30 +185,25 @@ void init_timer(platform_timer *timer) } #if defined (ARM_NPU) - -static void _reset_ethosu_counters(void) +static void _reset_ethosu_counters() { /* Reset all cycle and event counters. */ - ETHOSU_PMU_CYCCNT_Reset(); - ETHOSU_PMU_EVCNTR_ALL_Reset(); + ETHOSU_PMU_CYCCNT_Reset(ðosu_drv); + ETHOSU_PMU_EVCNTR_ALL_Reset(ðosu_drv); } - -static void _init_ethosu_cyclecounter(void) +static void _init_ethosu_cyclecounter() { /* Reset overflow status. */ - ETHOSU_PMU_Set_CNTR_OVS(ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CCNT_Msk); - + ETHOSU_PMU_Set_CNTR_OVS(ðosu_drv, ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CCNT_Msk); /* We can retrieve only 4 PMU counters: */ - ETHOSU_PMU_Set_EVTYPER(0, ETHOSU_PMU_NPU_IDLE); - ETHOSU_PMU_Set_EVTYPER(1, ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED); - ETHOSU_PMU_Set_EVTYPER(2, ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN); - ETHOSU_PMU_Set_EVTYPER(3, ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED); - + ETHOSU_PMU_Set_EVTYPER(ðosu_drv, 0, ETHOSU_PMU_NPU_IDLE); + ETHOSU_PMU_Set_EVTYPER(ðosu_drv, 1, ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED); + ETHOSU_PMU_Set_EVTYPER(ðosu_drv, 2, ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN); + ETHOSU_PMU_Set_EVTYPER(ðosu_drv, 3, ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED); /* Enable PMU. */ - ETHOSU_PMU_Enable(); - + ETHOSU_PMU_Enable(ðosu_drv); /* Enable counters for cycle and counter# 0. */ - ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CNT2_Msk | ETHOSU_PMU_CNT3_Msk | ETHOSU_PMU_CNT4_Msk| ETHOSU_PMU_CCNT_Msk); + ETHOSU_PMU_CNTR_Enable(ðosu_drv, ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CNT2_Msk | ETHOSU_PMU_CNT3_Msk | ETHOSU_PMU_CNT4_Msk| ETHOSU_PMU_CCNT_Msk); _reset_ethosu_counters(); } @@ -235,7 +232,7 @@ static uint32_t counter_overflow(uint32_t pmu_counter_mask) { /* Check for overflow: The idle counter is 32 bit while the total cycle count is 64 bit. */ - const uint32_t overflow_status = ETHOSU_PMU_Get_CNTR_OVS(); + const uint32_t overflow_status = ETHOSU_PMU_Get_CNTR_OVS(ðosu_drv); return pmu_counter_mask & overflow_status; } @@ -298,11 +295,11 @@ static time_counter bm_get_time_counter(void) .counter = get_time_counter(), #if defined (ARM_NPU) - .npu_total_ccnt = ETHOSU_PMU_Get_CCNTR(), - .npu_idle_ccnt = ETHOSU_PMU_Get_EVCNTR(0), - .npu_axi0_read_beats = ETHOSU_PMU_Get_EVCNTR(1), - .npu_axi0_write_beats = ETHOSU_PMU_Get_EVCNTR(2), - .npu_axi1_read_beats = ETHOSU_PMU_Get_EVCNTR(3) + .npu_total_ccnt = ETHOSU_PMU_Get_CCNTR(ðosu_drv), + .npu_idle_ccnt = ETHOSU_PMU_Get_EVCNTR(ðosu_drv, 0), + .npu_axi0_read_beats = ETHOSU_PMU_Get_EVCNTR(ðosu_drv, 1), + .npu_axi0_write_beats = ETHOSU_PMU_Get_EVCNTR(ðosu_drv, 2), + .npu_axi1_read_beats = ETHOSU_PMU_Get_EVCNTR(ðosu_drv, 3) #endif /* defined (ARM_NPU) */ }; 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