From 661959c6d2fabada5d465e9de8f84128e3f7b684 Mon Sep 17 00:00:00 2001 From: Kshitij Sisodia Date: Wed, 24 Nov 2021 10:39:52 +0000 Subject: MLECO-2426: Support for new Corstone-300 app note AN552 rev B. These changes will limit the use of FPGA internal SRAM from a max of 4MiB to 2MiB and the BRAM from 2MiB to 1MiB. Change-Id: I69c8e695aee26ff4f235bfe83ffd26efbd66f547 --- set_up_default_resources.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'set_up_default_resources.py') diff --git a/set_up_default_resources.py b/set_up_default_resources.py index 3eff6bf..f364795 100755 --- a/set_up_default_resources.py +++ b/set_up_default_resources.py @@ -134,8 +134,8 @@ NPUConfig = namedtuple('NPUConfig',['config_name', 'ethos_u_npu_id', 'ethos_u_config_id']) -# The default internal SRAM size for Corstone-300 implementation on MPS3 -mps3_max_sram_sz = 4 * 1024 * 1024 # 4 MiB +# The internal SRAM size for Corstone-300 implementation on MPS3 specified by AN552 +mps3_max_sram_sz = 2 * 1024 * 1024 # 2 MiB (2 banks of 1 MiB each) def call_command(command: str) -> str: -- cgit v1.2.1