From 31ae9f09bb3535975595e999fbc7baca889e46e8 Mon Sep 17 00:00:00 2001 From: alexander Date: Thu, 10 Feb 2022 16:15:54 +0000 Subject: MLECO-2682: CMake and source refactoring. MLECO-2930: logging macros were extracted from hal.h and used separately around the code. MLECO-2931: arm_math lib introduced, cmsis-dsp removed from top level linkage. MLECO-2915: platform related post-build steps. Change-Id: Id718884e22f262a5c070ded3f3f5d4b048820147 Signed-off-by: alexander --- scripts/cmake/platforms/mps3/mps3-sse-300.sct | 145 ++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 scripts/cmake/platforms/mps3/mps3-sse-300.sct (limited to 'scripts/cmake/platforms/mps3/mps3-sse-300.sct') diff --git a/scripts/cmake/platforms/mps3/mps3-sse-300.sct b/scripts/cmake/platforms/mps3/mps3-sse-300.sct new file mode 100644 index 0000000..f78dc25 --- /dev/null +++ b/scripts/cmake/platforms/mps3/mps3-sse-300.sct @@ -0,0 +1,145 @@ +; Copyright (c) 2021 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping information. +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and +; the model should only be placed in those regions. +; +;--------------------------------------------------------- +; First load region (ITCM) +;--------------------------------------------------------- +LOAD_REGION_0 0x00000000 0x00080000 +{ + ;----------------------------------------------------- + ; First part of code mem - 512kiB + ;----------------------------------------------------- + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + * (InRoot$$Sections) + + ; Essentially only RO-CODE, RO-DATA is in a + ; different region. + .ANY (+RO) + } + + ;----------------------------------------------------- + ; 128kiB of 512kiB DTCM is used for any other RW or ZI + ; data. Note: this region is internal to the Cortex-M + ; CPU. + ;----------------------------------------------------- + dtcm.bin 0x20000000 0x00020000 + { + ; Any R/W and/or zero initialised data + .ANY(+RW +ZI) + } + + ;----------------------------------------------------- + ; 384kiB of stack space within the DTCM region. See + ; `dtcm.bin` for the first section. Note: by virtue of + ; being part of DTCM, this region is only accessible + ; from Cortex-M55. + ;----------------------------------------------------- + ARM_LIB_STACK 0x20020000 EMPTY ALIGN 8 0x00060000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. + ; This region should have 3 cycle read latency from + ; both Cortex-M55 and Ethos-U NPU + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + ; Cache area (if used) + *.o (.bss.NoInit.ethos_u_cache) + + ; activation buffers a.k.a tensor arena when + ; memory mode sram only or shared sram + *.o (.bss.NoInit.activation_buf_sram) + } +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + ; nn model's baked in input matrices + *.o (ifm) + + ; nn model's default space + *.o (nn_model) + + ; labels + *.o (labels) + + ; activation buffers a.k.a tensor arena when memory mode dedicated sram + *.o (activation_buf_dram) + } + + ;----------------------------------------------------- + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + ; Note: Total BRAM size available is 1MiB. + ;----------------------------------------------------- + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + .ANY (+RO-DATA) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} -- cgit v1.2.1