diff options
Diffstat (limited to 'source/hal/source/platform/mps3')
6 files changed, 219 insertions, 4 deletions
diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt index 5008f0b..2791150 100644 --- a/source/hal/source/platform/mps3/CMakeLists.txt +++ b/source/hal/source/platform/mps3/CMakeLists.txt @@ -1,5 +1,5 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -133,6 +133,18 @@ if (CPU_PROFILE_ENABLED) target_compile_definitions(${PLATFORM_DRIVERS_TARGET} PUBLIC CPU_PROFILE_ENABLED) endif() +# If Virtual Streaming Interface is enabled, we need to link the vsi driver +if (VSI_ENABLED) + target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + source/vsi_mps3.c) + add_subdirectory(${COMPONENTS_DIR}/vsi ${CMAKE_BINARY_DIR}/vsi) + + target_link_libraries(${PLATFORM_DRIVERS_TARGET} + PUBLIC + arm_vsi) +endif () + # If Ethos-U is enabled, we need the driver library too if (ETHOS_U_NPU_ENABLED) diff --git a/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h b/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h index 2085c6a..9fb7b9e 100644 --- a/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h +++ b/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -131,6 +131,14 @@ #define UARTRX5_IRQn (125) /* UART 5 RX Interrupt */ #define UARTTX5_IRQn (126) /* UART 5 TX Interrupt */ #define UART5_IRQn (127) /* UART 5 combined Interrupt */ +#define ARM_VSI0_IRQn (224) /* 224: VSI 0 */ +#define ARM_VSI1_IRQn (225) /* 225: VSI 1 */ +#define ARM_VSI2_IRQn (226) /* 226: VSI 2 */ +#define ARM_VSI3_IRQn (227) /* 227: VSI 3 */ +#define ARM_VSI4_IRQn (228) /* 228: VSI 4 */ +#define ARM_VSI5_IRQn (229) /* 229: VSI 5 */ +#define ARM_VSI6_IRQn (230) /* 230: VSI 6 */ +#define ARM_VSI7_IRQn (231) /* 231: VSI 7 */ /* #undef HDCLCD_IRQn */ #endif /* PERIPHERAL_IRQS_H */ diff --git a/source/hal/source/platform/mps3/include/sse-310/peripheral_irqs.h b/source/hal/source/platform/mps3/include/sse-310/peripheral_irqs.h index 95b62c7..0414f63 100644 --- a/source/hal/source/platform/mps3/include/sse-310/peripheral_irqs.h +++ b/source/hal/source/platform/mps3/include/sse-310/peripheral_irqs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -129,6 +129,14 @@ #define UARTRX5_IRQn (125) /* UART 5 RX Interrupt */ #define UARTTX5_IRQn (126) /* UART 5 TX Interrupt */ #define UART5_IRQn (127) /* UART 5 combined Interrupt */ +#define ARM_VSI0_IRQn (224) /* 224: VSI 0 */ +#define ARM_VSI1_IRQn (225) /* 225: VSI 1 */ +#define ARM_VSI2_IRQn (226) /* 226: VSI 2 */ +#define ARM_VSI3_IRQn (227) /* 227: VSI 3 */ +#define ARM_VSI4_IRQn (228) /* 228: VSI 4 */ +#define ARM_VSI5_IRQn (229) /* 229: VSI 5 */ +#define ARM_VSI6_IRQn (230) /* 230: VSI 6 */ +#define ARM_VSI7_IRQn (231) /* 231: VSI 7 */ /* #undef HDCLCD_IRQn */ #endif /* PERIPHERAL_IRQS_H */ diff --git a/source/hal/source/platform/mps3/include/vsi_mps3.h b/source/hal/source/platform/mps3/include/vsi_mps3.h new file mode 100644 index 0000000..a8895ea --- /dev/null +++ b/source/hal/source/platform/mps3/include/vsi_mps3.h @@ -0,0 +1,115 @@ +/* + * SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef VSI_MPS3_H +#define VSI_MPS3_H + +#include <stdint.h> +#include <stdbool.h> + +#include "peripheral_irqs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __IM +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#endif +#ifndef __OM +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#endif +#ifndef __IOM +#define __IOM volatile /*! Defines 'read/write' structure member permissions */ +#endif + +/// Structure type to access the virtual streaming interface +typedef struct +{ + /// Interrupt Request (IRQ) + struct { + __IOM uint32_t Enable; /*!< (R/W) IRQ Enable */ + __OM uint32_t Set; /*!< (-/W) IRQ Set */ + __OM uint32_t Clear; /*!< (-/W) IRQ Clear */ + __IM uint32_t Status; /*!< (R/-) IRQ Status */ + } IRQ; + uint32_t reserved1[60]; + /// Time counter with 1MHz input frequency + struct { + __IOM uint32_t Control; /*!< (R/W) Timer Control */ + __IOM uint32_t Interval; /*!< (R/W) Timer Interval Value (in microseconds) */ + __IM uint32_t Count; /*!< (R/-) Timer Overflow Count */ + } Timer; + uint32_t reserved2[61]; + /// Direct Memory Access (DMA) Controller + struct { + __IOM uint32_t Control; /*!< (R/W) DMA Control */ + __IOM uint32_t Address; /*!< (R/W) DMA Memory Start Address */ + __IOM uint32_t BlockSize; /*!< (R/W) DMA Block Size (in bytes, multiple of 4) */ + __IOM uint32_t BlockNum; /*!< (R/W) DMA Number of Blocks (must be 2^n) */ + __IM uint32_t BlockIndex; /*!< (R/-) DMA Block Index */ + } DMA; + uint32_t reserved3[59]; + __IOM uint32_t Regs[64]; /*!< (R/W) User Registers */ +} ARM_VSI_Type; + +/* VSI Timer Control Definitions for Timer.Control register */ +#define ARM_VSI_Timer_Run_Pos 0U /*!< Timer Control: Run Position */ +#define ARM_VSI_Timer_Run_Msk (1UL << ARM_VSI_Timer_Run_Pos) /*!< Timer Control: Run Mask */ +#define ARM_VSI_Timer_Periodic_Pos 1U /*!< Timer Control: Periodic Position */ +#define ARM_VSI_Timer_Periodic_Msk (1UL << ARM_VSI_Timer_Periodic_Pos) /*!< Timer Control: Periodic Mask */ +#define ARM_VSI_Timer_Trig_IRQ_Pos 2U /*!< Timer Control: Trig_IRQ Position */ +#define ARM_VSI_Timer_Trig_IRQ_Msk (1UL << ARM_VSI_Timer_Trig_IRQ_Pos) /*!< Timer Control: Trig_IRQ Mask */ +#define ARM_VSI_Timer_Trig_DMA_Pos 3U /*!< Timer Control: Trig_DAM Position */ +#define ARM_VSI_Timer_Trig_DMA_Msk (1UL << ARM_VSI_Timer_Trig_DMA_Pos) /*!< Timer Control: Trig_DMA Mask */ + +/* VSI DMA Control Definitions for DMA.Control register */ +#define ARM_VSI_DMA_Enable_Pos 0U /*!< DMA Control: Enable Position */ +#define ARM_VSI_DMA_Enable_Msk (1UL << ARM_VSI_DMA_Enable_Pos) /*!< DMA Control: Enable Mask */ +#define ARM_VSI_DMA_Direction_Pos 1U /*!< DMA Control: Direction Position */ +#define ARM_VSI_DMA_Direction_Msk (1UL << ARM_VSI_DMA_Direction_Pos) /*!< DMA Control: Direction Mask */ +#define ARM_VSI_DMA_Direction_P2M (0UL*ARM_VSI_DMA_Direction_Msk) /*!< DMA Control: Direction P2M */ +#define ARM_VSI_DMA_Direction_M2P (1UL*ARM_VSI_DMA_Direction_Msk) /*!< DMA Control: Direction M2P */ + +/* Memory mapping of 8 VSI peripherals */ +#define ARM_VSI0_BASE (0x4FF00000UL) /*!< VSI 0 Base Address */ +#define ARM_VSI1_BASE (0x4FF10000UL) /*!< VSI 1 Base Address */ +#define ARM_VSI2_BASE (0x4FF20000UL) /*!< VSI 2 Base Address */ +#define ARM_VSI3_BASE (0x4FF30000UL) /*!< VSI 3 Base Address */ +#define ARM_VSI4_BASE (0x4FF40000UL) /*!< VSI 4 Base Address */ +#define ARM_VSI5_BASE (0x4FF50000UL) /*!< VSI 5 Base Address */ +#define ARM_VSI6_BASE (0x4FF60000UL) /*!< VSI 6 Base Address */ +#define ARM_VSI7_BASE (0x4FF70000UL) /*!< VSI 7 Base Address */ +#define ARM_VSI0 ((ARM_VSI_Type *)ARM_VSI0_BASE) /*!< VSI 0 struct */ +#define ARM_VSI1 ((ARM_VSI_Type *)ARM_VSI1_BASE) /*!< VSI 1 struct */ +#define ARM_VSI2 ((ARM_VSI_Type *)ARM_VSI2_BASE) /*!< VSI 2 struct */ +#define ARM_VSI3 ((ARM_VSI_Type *)ARM_VSI3_BASE) /*!< VSI 3 struct */ +#define ARM_VSI4 ((ARM_VSI_Type *)ARM_VSI4_BASE) /*!< VSI 4 struct */ +#define ARM_VSI5 ((ARM_VSI_Type *)ARM_VSI5_BASE) /*!< VSI 5 struct */ +#define ARM_VSI6 ((ARM_VSI_Type *)ARM_VSI6_BASE) /*!< VSI 6 struct */ +#define ARM_VSI7 ((ARM_VSI_Type *)ARM_VSI7_BASE) /*!< VSI 7 struct */ + +/** + * @brief Initialises the VSI + * @return 0 if successful, error code otherwise + **/ +int vsi_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* VSI_MPS3_H */ diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c index 73b388b..1f55bb9 100644 --- a/source/hal/source/platform/mps3/source/platform_drivers.c +++ b/source/hal/source/platform/mps3/source/platform_drivers.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ #endif /* ARM_NPU */ +#if VSI_ENABLED +#include "vsi_mps3.h" +#endif /* VSI_ENABLED */ + /** * @brief Checks if the platform is valid by checking * the CPU ID for the FPGA implementation against @@ -94,6 +98,12 @@ int platform_init(void) #endif /* ARM_NPU */ +#if VSI_ENABLED + if (0 != (err = vsi_init())) { + return err; + } +#endif /* VSI_ENABLED */ + /* Print target design info */ info("Target system design: %s\n", s_platform_name); return 0; diff --git a/source/hal/source/platform/mps3/source/vsi_mps3.c b/source/hal/source/platform/mps3/source/vsi_mps3.c new file mode 100644 index 0000000..8516c1c --- /dev/null +++ b/source/hal/source/platform/mps3/source/vsi_mps3.c @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "vsi_mps3.h" + +#include "log_macros.h" +#include "RTE_Components.h" +#include "peripheral_irqs.h" + +#include "video_drv.h" + +/* Exception / Interrupt Handler */ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK __NO_RETURN handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) + +int vsi_init(void) +{ + /* Register the VSI handlers in our vector table. */ + NVIC_SetVector(ARM_VSI0_IRQn, (uint32_t)ARM_VSI0_Handler); + NVIC_SetVector(ARM_VSI1_IRQn, (uint32_t)ARM_VSI1_Handler); + NVIC_SetVector(ARM_VSI2_IRQn, (uint32_t)ARM_VSI2_Handler); + NVIC_SetVector(ARM_VSI3_IRQn, (uint32_t)ARM_VSI3_Handler); + NVIC_SetVector(ARM_VSI4_IRQn, (uint32_t)ARM_VSI4_Handler); + NVIC_SetVector(ARM_VSI5_IRQn, (uint32_t)ARM_VSI5_Handler); + NVIC_SetVector(ARM_VSI6_IRQn, (uint32_t)ARM_VSI6_Handler); + NVIC_SetVector(ARM_VSI7_IRQn, (uint32_t)ARM_VSI7_Handler); + + /* Initialize Video VSI. */ + if (VideoDrv_Initialize(NULL) != VIDEO_DRV_OK) { + printf_err("Failed to initialise video driver\n"); + return 1; + } + + info("VSI device initialised\n"); + + return 0; +} |