summaryrefslogtreecommitdiff
path: root/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3
diff options
context:
space:
mode:
Diffstat (limited to 'source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3')
-rw-r--r--source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c4
-rw-r--r--source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/timer_mps3.c12
-rw-r--r--source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c5
3 files changed, 13 insertions, 8 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c
index f4f2e6b..7040cf3 100644
--- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c
+++ b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c
@@ -19,6 +19,8 @@
#include "bsp_core_log.h"
#include "smm_mps3.h"
+#include <inttypes.h>
+
uint32_t GetMPS3CoreClock(void)
{
const uint32_t default_clock = 32000000;
@@ -28,7 +30,7 @@ uint32_t GetMPS3CoreClock(void)
}
if (!warned_once) {
- warn("MPS3_SCC->CFG_ACLK reads 0. Assuming default clock of %u\n",
+ warn("MPS3_SCC->CFG_ACLK reads 0. Assuming default clock of %" PRIu32 "\n",
default_clock);
warned_once = 1;
}
diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/timer_mps3.c b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/timer_mps3.c
index 0a3a8b1..a72103c 100644
--- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/timer_mps3.c
+++ b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/timer_mps3.c
@@ -19,6 +19,8 @@
#include "bsp_core_log.h"
#include "device_mps3.h"
+#include <inttypes.h>
+
void timer_reset(void)
{
MPS3_FPGAIO->CLK1HZ = 0;
@@ -39,11 +41,11 @@ mps3_time_counter get_time_counter(void)
.counter_fpga = MPS3_FPGAIO->COUNTER,
.counter_systick = Get_SysTick_Cycle_Count()
};
- debug("Timestamp:\
- \n\tCounter 1 Hz: %u\
- \n\tCounter 100 Hz: %u\
- \n\tCounter FPGA: %u\
- \n\tCounter CPU: %llu\n",
+ debug("Timestamp:"
+ "\n\tCounter 1 Hz: %" PRIu32
+ "\n\tCounter 100 Hz: %" PRIu32
+ "\n\tCounter FPGA: %" PRIu32
+ "\n\tCounter CPU: %" PRIu64 "\n",
t.counter_1Hz, t.counter_100Hz, t.counter_fpga, t.counter_systick);
return t;
}
diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c
index 1bf8291..ed12c8b 100644
--- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c
+++ b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c
@@ -107,10 +107,11 @@ bool GetLine(char *lp, unsigned int len)
return false;
case CR: /* CR - done, stop editing line. */
- *lp = c;
+ UartPutc (*lp = c); /* Echo and store character. */
lp++; /* Increment line pointer */
cnt++; /* and count. */
c = LF;
+ break;
default:
UartPutc (*lp = c); /* Echo and store character. */
fflush (stdout);
@@ -124,7 +125,7 @@ bool GetLine(char *lp, unsigned int len)
return true;
}
-void UartEndSimulation(int code)
+__attribute__((noreturn)) void UartEndSimulation(int code)
{
UartPutc((char) 0x4); /* End of simulation */
UartPutc((char) code); /* End of simulation */