diff options
Diffstat (limited to 'scripts/cmake')
-rw-r--r-- | scripts/cmake/cmsis-dsp.cmake | 2 | ||||
-rw-r--r-- | scripts/cmake/common_user_options.cmake | 2 | ||||
-rw-r--r-- | scripts/cmake/platforms/mps3/build_configuration.cmake | 37 | ||||
-rw-r--r-- | scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.ld (renamed from scripts/cmake/platforms/mps3/mps3-sse-300.ld) | 0 | ||||
-rw-r--r-- | scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.sct (renamed from scripts/cmake/platforms/mps3/mps3-sse-300.sct) | 0 | ||||
-rw-r--r-- | scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld | 214 | ||||
-rw-r--r-- | scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct | 140 | ||||
-rw-r--r-- | scripts/cmake/tensorflow.cmake | 11 | ||||
-rw-r--r-- | scripts/cmake/toolchains/bare-metal-armclang.cmake | 22 | ||||
-rw-r--r-- | scripts/cmake/toolchains/bare-metal-gcc.cmake | 24 |
10 files changed, 436 insertions, 16 deletions
diff --git a/scripts/cmake/cmsis-dsp.cmake b/scripts/cmake/cmsis-dsp.cmake index f2de158..73f6100 100644 --- a/scripts/cmake/cmsis-dsp.cmake +++ b/scripts/cmake/cmsis-dsp.cmake @@ -69,7 +69,7 @@ if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU") endif () # 5. Add any custom/conditional flags for compilation or linkage -if (${CMAKE_SYSTEM_PROCESSOR} STREQUAL cortex-m55) +if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55" OR "${CMAKE_SYSTEM_ARCH}" STREQUAL "armv8.1-m.main") target_compile_definitions(${CMSIS_DSP_TARGET} PUBLIC ARM_MATH_MVEI ARM_MATH_DSP diff --git a/scripts/cmake/common_user_options.cmake b/scripts/cmake/common_user_options.cmake index 7dc68de..7981068 100644 --- a/scripts/cmake/common_user_options.cmake +++ b/scripts/cmake/common_user_options.cmake @@ -43,7 +43,7 @@ USER_OPTION(TARGET_PLATFORM "Target platform to execute evaluation application: mps3 STRING) -USER_OPTION(TARGET_SUBSYSTEM "Specify platform target subsystem: sse-300 or none" +USER_OPTION(TARGET_SUBSYSTEM "Specify platform target subsystem: sse-300, sse-310 or none" sse-300 STRING) diff --git a/scripts/cmake/platforms/mps3/build_configuration.cmake b/scripts/cmake/platforms/mps3/build_configuration.cmake index 76c9e78..6e21d9b 100644 --- a/scripts/cmake/platforms/mps3/build_configuration.cmake +++ b/scripts/cmake/platforms/mps3/build_configuration.cmake @@ -17,11 +17,35 @@ function(set_platform_global_defaults) message(STATUS "Platform: MPS3 FPGA Prototyping Board or FVP") + + if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR) + if (TARGET_SUBSYSTEM STREQUAL sse-300) + set(CMAKE_SYSTEM_PROCESSOR cortex-m55 CACHE STRING "Cortex-M CPU to use") + elseif(TARGET_SUBSYSTEM STREQUAL sse-310) + # For CMake versions older than 3.21, the compiler and linker flags for + # ArmClang are added by CMake automatically which makes it mandatory to + # define the system processor. For CMake versions 3.21 or later (that + # implement policy CMP0123) we use armv8.1-m as the arch until the + # toolchain officially supports Cortex-M85. For older version of CMake + # we revert to using Cortex-M55 as the processor (as this will work + # for M85 too). + if(POLICY CMP0123) + set(CMAKE_SYSTEM_ARCH armv8.1-m.main CACHE STRING "System arch to use") + else() + set(CMAKE_SYSTEM_PROCESSOR cortex-m55) + endif() + endif() + endif() + if (NOT DEFINED CMAKE_TOOLCHAIN_FILE) set(CMAKE_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/bare-metal-gcc.cmake CACHE FILEPATH "Toolchain file") endif() + if ((ETHOS_U_NPU_ID STREQUAL U65) AND (TARGET_SUBSYSTEM STREQUAL sse-310)) + message(FATAL_ERROR "Non compatible Ethos-U NPU processor ${ETHOS_U_NPU_ID} and target subsystem ${TARGET_SUBSYSTEM}") + endif() + set(LINKER_SCRIPT_NAME "mps3-${TARGET_SUBSYSTEM}" PARENT_SCOPE) set(PLATFORM_DRIVERS_DIR "${HAL_PLATFORM_DIR}/mps3" PARENT_SCOPE) @@ -35,7 +59,7 @@ function(platform_custom_post_build) # Add link options for the linker script to be used: add_linker_script( ${PARSED_TARGET_NAME} # Target - ${CMAKE_SCRIPTS_DIR}/platforms/mps3 # Directory path + ${CMAKE_SCRIPTS_DIR}/platforms/mps3/${TARGET_SUBSYSTEM} # Directory path ${LINKER_SCRIPT_NAME}) # Name of the file without suffix add_target_map_file( @@ -48,8 +72,13 @@ function(platform_custom_post_build) file(REMOVE_RECURSE ${SECTORS_BIN_DIR}) file(MAKE_DIRECTORY ${SECTORS_BIN_DIR}) - set(LINKER_SECTION_TAGS "*.at_itcm" "*.at_ddr") - set(LINKER_OUTPUT_BIN_TAGS "itcm.bin" "ddr.bin") + if (TARGET_SUBSYSTEM STREQUAL sse-310) + set(LINKER_SECTION_TAGS "*.at_bram" "*.at_ddr") + set(LINKER_OUTPUT_BIN_TAGS "bram.bin" "ddr.bin") + else() + set(LINKER_SECTION_TAGS "*.at_itcm" "*.at_ddr") + set(LINKER_OUTPUT_BIN_TAGS "itcm.bin" "ddr.bin") + endif() add_bin_generation_command( TARGET_NAME ${PARSED_TARGET_NAME} @@ -64,4 +93,4 @@ function(platform_custom_post_build) POST_BUILD COMMAND ${CMAKE_COMMAND} -E copy ${MPS3_FPGA_CONFIG} ${SECTORS_DIR}) -endfunction()
\ No newline at end of file +endfunction() diff --git a/scripts/cmake/platforms/mps3/mps3-sse-300.ld b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.ld index 3e930a0..3e930a0 100644 --- a/scripts/cmake/platforms/mps3/mps3-sse-300.ld +++ b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.ld diff --git a/scripts/cmake/platforms/mps3/mps3-sse-300.sct b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.sct index 0a38778..0a38778 100644 --- a/scripts/cmake/platforms/mps3/mps3-sse-300.sct +++ b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.sct diff --git a/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld new file mode 100644 index 0000000..a631aaa --- /dev/null +++ b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +__STACK_SIZE = 0x00008000; +__HEAP_SIZE = 0x000C0000; + +/* System memory brief */ +MEMORY +{ + ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 + DTCM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000 + SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000 + DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000 + + /* Dynamic load regions declared for use by FVP only + * These regions are mentioned in the CMake subsystem profile. + * Do not change the addresses here in isolation. */ + DDR_dynamic_model (rx) : ORIGIN = 0x90000000, LENGTH = 0x02000000 + DDR_dynamic_ifm (rx) : ORIGIN = 0x92000000, LENGTH = 0x01000000 + DDR_dynamic_ofm (rx) : ORIGIN = 0x93000000, LENGTH = 0x01000000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions ITCM and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text.at_bram : + { + KEEP(*(.vectors)) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + KEEP(*(.eh_frame*)) + + *(vtable) + *(.data) + *(.data.*) + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + KEEP(*(.jcr*)) + . = ALIGN(4); + + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + + *(.rodata*) + . = ALIGN(4); + * (npu_driver_version) + . = ALIGN(4); + * (npu_driver_arch_version) + . = ALIGN(4); + + __copy_table_start__ = .; + . = ALIGN(4); + __copy_table_end__ = .; + } > BRAM + + __exidx_start = .; + .ARM.exidx.at_bram : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > BRAM + __exidx_end = .; + + .sram : + { + . = ALIGN(16); + /* Cache area (if used) */ + *(.bss.NoInit.ethos_u_cache) + . = ALIGN (16); + /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */ + *(.bss.NoInit.activation_buf_sram) + . = ALIGN(16); + } > SRAM AT > SRAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > BRAM + + .zero.table.at_bram : + { + . = ALIGN(4); + __zero_table_start__ = .; + + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */ + + __zero_table_end__ = .; + } > BRAM + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > BRAM + + __bram_total = ALIGN(4); + + ASSERT( __bram_total < (ORIGIN(BRAM) + LENGTH(BRAM)), "BRAM overflow") + + .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM + PROVIDE(__stack = __StackTop); + ASSERT(__STACK_SIZE <= LENGTH(DTCM), "DTCM overflow") + + .ddr.at_ddr : + { + /* __attribute__((aligned(16))) is not handled by the CMSIS startup code. + * Force the alignment here as a workaround */ + . = ALIGN(16); + /* nn model's baked in input matrices */ + *(ifm) + . = ALIGN(16); + /* nn model's default space */ + *(nn_model) + . = ALIGN (16); + /* labels */ + *(labels) + . = ALIGN (16); + /* activation buffers a.k.a tensor arena when memory mode dedicated sram */ + *(activation_buf_dram) + . = ALIGN (16); + } > DDR AT > DDR + +} diff --git a/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct new file mode 100644 index 0000000..452b0fe --- /dev/null +++ b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct @@ -0,0 +1,140 @@ +; Copyright (c) 2021 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping +; information. +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should +; only be placed in those regions. +; + +;--------------------------------------------------------- +; First load region (SRAM/BRAM) 2MiB region +;--------------------------------------------------------- +LOAD_REGION_0 0x11000000 0x00200000 +{ + ;----------------------------------------------------- + ; 0.5 MiB of SRAM/BRAM region. Our vector table also + ; resides here as the default INITSVTOR is 0x11000000. + ; We currently do not use the ITCM for any code, but + ; could potentially put some critical code in there + ; if we need to. + ;----------------------------------------------------- + bram.bin 0x11000000 0x00080000 + { + *.o (RESET, +First) + * (InRoot$$Sections) + + ; Essentially only RO (code + data) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Next 0.5 MiB of SRAM/BRAM region for RO, RW and ZI + ; data, 8 byte aligned. + ;----------------------------------------------------- + data.bin 0x11080000 ALIGN 8 0x00080000 + { + ; Any RO-DATA + .ANY (+RO-DATA) + + ; Any R/W and/or zero initialised data + .ANY(+RW +ZI) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x11100000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; 32 kiB of stack space occupying the DTCM region. + ;----------------------------------------------------- + ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. The total memory is 4 MiB (we are choosing + ; to not use the other bank). This region should have + ; 3 cycle read latency from both CPU and Ethos-U NPU. + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + ; Cache area (if used) + *.o (.bss.NoInit.ethos_u_cache) + + ; activation buffers a.k.a tensor arena when + ; memory mode sram only or shared sram + *.o (.bss.NoInit.activation_buf_sram) + } +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + ; nn model's baked in input matrices + *.o (ifm) + + ; nn model's default space + *.o (nn_model) + + ; labels + *.o (labels) + + ; activation buffers a.k.a tensor arena when memory mode dedicated sram + *.o (activation_buf_dram) + } + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} diff --git a/scripts/cmake/tensorflow.cmake b/scripts/cmake/tensorflow.cmake index 2374c86..8a790bc 100644 --- a/scripts/cmake/tensorflow.cmake +++ b/scripts/cmake/tensorflow.cmake @@ -50,7 +50,16 @@ if (TARGET_PLATFORM STREQUAL native) set(TENSORFLOW_LITE_MICRO_TARGET_ARCH x86_64) else() set(TENSORFLOW_LITE_MICRO_TARGET "cortex_m_generic") - set(TENSORFLOW_LITE_MICRO_TARGET_ARCH ${CMAKE_SYSTEM_PROCESSOR}${CPU_FEATURES}) + + if ("${CMAKE_SYSTEM_ARCH}" STREQUAL "armv8.1-m.main") + # TensorFlow's generic makefile doesn't currently have a flow for Cortex-M85. + # We build for Arm Cortex-M55 instead. + # @TODO: check with latest TensorFlow package. + set(TENSORFLOW_LITE_MICRO_TARGET_ARCH "cortex-m55") + else() + set(TENSORFLOW_LITE_MICRO_TARGET_ARCH "${CMAKE_SYSTEM_PROCESSOR}") + endif() + if(ETHOS_U_NPU_ENABLED) # Arm Ethos-U55 NPU is the co-processor for ML workload: set(TENSORFLOW_LITE_MICRO_CO_PROCESSOR "ethos_u") diff --git a/scripts/cmake/toolchains/bare-metal-armclang.cmake b/scripts/cmake/toolchains/bare-metal-armclang.cmake index d0b0824..97da76f 100644 --- a/scripts/cmake/toolchains/bare-metal-armclang.cmake +++ b/scripts/cmake/toolchains/bare-metal-armclang.cmake @@ -31,7 +31,7 @@ set(MIN_ARM_CLANG_VERSION 6.16) set(CMAKE_C_COMPILER_WORKS 1) set(CMAKE_CXX_COMPILER_WORKS 1) -if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR) +if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR AND NOT DEFINED CMAKE_SYSTEM_ARCH) set(CMAKE_SYSTEM_PROCESSOR cortex-m55) endif() @@ -39,13 +39,27 @@ if (CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m55) # Flags for cortex-m55 set(CPU_ID M55) set(CPU_COMPILE_DEF CPU_CORTEX_${CPU_ID}) - set(CPU_NAME ${CMAKE_SYSTEM_PROCESSOR}) set(ARM_CPU "ARMC${CPU_ID}") set(FLOAT_ABI hard) set(ARM_MATH_DSP 1) set(ARM_MATH_LOOPUNROLL 1) set(CPU_HEADER_FILE "${ARM_CPU}.h") + set(CPU_COMPILE_OPTION "-mcpu=${CMAKE_SYSTEM_PROCESSOR}") set(CPU_LINK_OPT "--cpu=Cortex-${CPU_ID}") +elseif (CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m85 OR CMAKE_SYSTEM_ARCH STREQUAL armv8.1-m.main) + # Flags for Cortex-M85 + set(CPU_ID ARMv81MML_DSP_DP_MVE_FP) + set(ARM_CPU "ARMv81MML") + set(CPU_COMPILE_DEF ${CPU_ID}) + set(FLOAT_ABI hard) + set(ARM_MATH_DSP 1) + set(ARM_MATH_LOOPUNROLL 1) + + # @TODO: Revise once we have the CPU file in CMSIS and CPU flags + # are supported by toolchains. + set(CPU_HEADER_FILE "${CPU_ID}.h") + set(CPU_COMPILE_OPTION "-march=armv8.1-m.main+mve.fp+fp.dp") + set(CPU_LINK_OPT "--cpu=8.1-M.Main.mve.fp") elseif(CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m33) # Flags for cortex-m33 to go here endif() @@ -67,11 +81,11 @@ add_compile_options( # Arch compile options: add_compile_options( -mthumb - -mcpu=${CPU_NAME} -mfloat-abi=${FLOAT_ABI} --target=arm-arm-non-eabi -mlittle-endian - -MD) + -MD + ${CPU_COMPILE_OPTION}) # Compile definitions: add_compile_definitions( diff --git a/scripts/cmake/toolchains/bare-metal-gcc.cmake b/scripts/cmake/toolchains/bare-metal-gcc.cmake index a5688d6..a6d6c0e 100644 --- a/scripts/cmake/toolchains/bare-metal-gcc.cmake +++ b/scripts/cmake/toolchains/bare-metal-gcc.cmake @@ -29,7 +29,7 @@ set(MIN_GCC_VERSION 10.2.1) set(CMAKE_C_COMPILER_WORKS 1) set(CMAKE_CXX_COMPILER_WORKS 1) -if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR) +if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR AND NOT DEFINED CMAKE_SYSTEM_ARCH) set(CMAKE_SYSTEM_PROCESSOR cortex-m55) endif() @@ -37,13 +37,27 @@ if (CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m55) # Flags for cortex-m55 set(CPU_ID M55) set(CPU_COMPILE_DEF CPU_CORTEX_${CPU_ID}) - set(CPU_NAME ${CMAKE_SYSTEM_PROCESSOR}) set(ARM_CPU "ARMC${CPU_ID}") set(FLOAT_ABI hard) set(ARM_MATH_DSP 1) set(ARM_MATH_LOOPUNROLL 1) set(CPU_HEADER_FILE "${ARM_CPU}.h") + set(CPU_COMPILE_OPTION "-mcpu=${CMAKE_SYSTEM_PROCESSOR}") set(CPU_LINK_OPT "--cpu=Cortex-${CPU_ID}") +elseif (CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m85 OR CMAKE_SYSTEM_ARCH STREQUAL armv8.1-m.main) + # Flags for Cortex-M85 + set(CPU_ID ARMv81MML_DSP_DP_MVE_FP) + set(ARM_CPU "ARMv81MML") + set(CPU_COMPILE_DEF ${CPU_ID}) + set(FLOAT_ABI hard) + set(ARM_MATH_DSP 1) + set(ARM_MATH_LOOPUNROLL 1) + + # @TODO: Revise once we have the CPU file in CMSIS and CPU flags + # are supported by toolchains. + set(CPU_HEADER_FILE "${CPU_ID}.h") + set(CPU_COMPILE_OPTION "-march=armv8.1-m.main+mve.fp+fp.dp") + set(CPU_LINK_OPT "--cpu=8.1-M.Main.mve.fp") elseif(CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m33) # Flags for cortex-m33 to go here endif() @@ -67,10 +81,10 @@ add_compile_options( # Arch compile options: add_compile_options( -mthumb - -mcpu=${CPU_NAME} -mfloat-abi=${FLOAT_ABI} -mlittle-endian - -MD) + -MD + ${CPU_COMPILE_OPTION}) # Compile definitions: add_compile_definitions( @@ -82,7 +96,7 @@ add_compile_definitions( # Link options: add_link_options( -mthumb - -mcpu=${CPU_NAME} + ${CPU_COMPILE_OPTION} -mfloat-abi=${FLOAT_ABI} -mlittle-endian --stats |