diff options
12 files changed, 89 insertions, 102 deletions
diff --git a/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake b/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake index 6fca4b3..37785e3 100644 --- a/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake +++ b/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake @@ -1,5 +1,6 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2021 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2021, 2024 Arm Limited and/or its +# affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,12 +17,15 @@ #---------------------------------------------------------------------------- #---------------------------------------------------------------------------- -# CMake description file for the Ethos-U55 Timing Adapter settings (single +# CMake description file for the Arm Ethos-U55 Timing Adapter settings (single # NPU core with two AXIs). #---------------------------------------------------------------------------- -set(TA0_BASE "${SEC_ETHOS_U_NPU_TA0_BASE}" CACHE STRING "Timing adapter 0: base-address") -set(TA1_BASE "${SEC_ETHOS_U_NPU_TA1_BASE}" CACHE STRING "Timing adapter 1: base-address") +# The platform CMake infra should set the base register values for +# TA component to work. For Ethos-U55, we need two base addresses. +if (NOT DEFINED TA0_BASE OR NOT DEFINED TA1_BASE) + message(FATAL_ERROR "TA0_BASE and TA1_BASE need to be defined.") +endif () message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.") diff --git a/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake b/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake index 9edf66e..e29d144 100644 --- a/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake +++ b/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake @@ -1,5 +1,6 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2021 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2021, 2024 Arm Limited and/or its +# affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,12 +17,15 @@ #---------------------------------------------------------------------------- #---------------------------------------------------------------------------- -# CMake description file for the Ethos-U55 Timing Adapter settings (single +# CMake description file for the Arm Ethos-U65 Timing Adapter settings (single # NPU core with two AXIs). #---------------------------------------------------------------------------- -set(TA0_BASE "${SEC_ETHOS_U_NPU_TA0_BASE}" CACHE STRING "Timing adapter 0: base-address") -set(TA1_BASE "${SEC_ETHOS_U_NPU_TA1_BASE}" CACHE STRING "Timing adapter 1: base-address") +# The platform CMake infra should set the base register values for +# TA component to work. For Ethos-U65, we need two base addresses. +if (NOT DEFINED TA0_BASE OR NOT DEFINED TA1_BASE) + message(FATAL_ERROR "TA0_BASE and TA1_BASE need to be defined.") +endif () message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.") diff --git a/source/hal/source/components/npu/CMakeLists.txt b/source/hal/source/components/npu/CMakeLists.txt index f2d2b08..eebf235 100644 --- a/source/hal/source/components/npu/CMakeLists.txt +++ b/source/hal/source/components/npu/CMakeLists.txt @@ -1,5 +1,6 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its +# affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -33,7 +34,8 @@ endif() # For the driver, we need to provide the CMSIS_PATH variable set(CMSIS_PATH ${CMSIS_SRC_PATH} CACHE PATH "Path to CMSIS directory") -# Definitions that will be set. +# Definitions that should be overridden by the platform wrapping this project. +# Otherwise, these defaults will be used. set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") set(ETHOS_U_IRQN "56" CACHE STRING "Ethos-U NPU Interrupt") set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enable") diff --git a/source/hal/source/components/npu/ethosu_npu_init.c b/source/hal/source/components/npu/ethosu_npu_init.c index dbee2ff..b7ed9c7 100644 --- a/source/hal/source/components/npu/ethosu_npu_init.c +++ b/source/hal/source/components/npu/ethosu_npu_init.c @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> - * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: Copyright 2022-2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -23,7 +23,22 @@ #include "ethosu_mem_config.h" /* Arm Ethos-U memory config */ #include "ethosu_driver.h" /* Arm Ethos-U driver header */ -struct ethosu_driver ethosu_drv; /* Default Ethos-U device driver */ +/* Mandatory definition checks. */ +#if !defined(ETHOS_U_BASE_ADDR) +#error "NPU base address is undefined." +#endif /* defnied(ETHOS_U_BASE_ADDR) */ + +#if !defined(ETHOS_U_IRQN) +#error "Arm NPU interrupt number is undefined." +#endif /* !defined(ETHOS_U_IRQN) */ + +#if !defined(ETHOS_U_SEC_ENABLED) +#error "Arm NPU security mode is undefined." +#endif /* !defined(ETHOS_U_SEC_ENABLED) */ + +#if !defined(ETHOS_U_PRIV_ENABLED) +#error "Arm NPU privilege mode is undefined." +#endif /* !defined(ETHOS_U_PRIV_ENABLED) */ #if defined(ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) static uint8_t cache_arena[ETHOS_U_CACHE_BUF_SZ] CACHE_BUF_ATTRIBUTE; @@ -31,6 +46,8 @@ static uint8_t cache_arena[ETHOS_U_CACHE_BUF_SZ] CACHE_BUF_ATTRIBUTE; static uint8_t *cache_arena = NULL; #endif /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */ +struct ethosu_driver ethosu_drv; /* Default Ethos-U device driver */ + static uint8_t *get_cache_arena() { return cache_arena; @@ -82,16 +99,15 @@ int arm_ethosu_npu_init(void) /* Initialise Ethos-U device */ void* const ethosu_base_address = (void *)(ETHOS_U_BASE_ADDR); - - if (0 != (err = ethosu_init( - ðosu_drv, /* Ethos-U driver device pointer */ - ethosu_base_address, /* Ethos-U NPU's base address. */ - get_cache_arena(), /* Pointer to fast mem area - NULL for U55. */ - get_cache_arena_size(), /* Fast mem region size. */ - ETHOS_U_SEC_ENABLED, /* Security enable. */ - ETHOS_U_PRIV_ENABLED))) /* Privilege enable. */ - { - printf_err("failed to initialise Ethos-U device\n"); + info("Initialising Ethos-U device@0x%" PRIx32 "\n", ETHOS_U_BASE_ADDR); + + if (0 != (err = ethosu_init(ðosu_drv, /* Ethos-U driver device pointer */ + ethosu_base_address, /* Ethos-U NPU's base address. */ + get_cache_arena(), /* Pointer to fast mem area - NULL for U55. */ + get_cache_arena_size(), /* Fast mem region size. */ + ETHOS_U_SEC_ENABLED, /* Security enable. */ + ETHOS_U_PRIV_ENABLED))) /* Privilege enable. */ { + printf_err("Failed to initialise Ethos-U device\n"); return err; } diff --git a/source/hal/source/components/npu_ta/CMakeLists.txt b/source/hal/source/components/npu_ta/CMakeLists.txt index 3778a14..9956384 100644 --- a/source/hal/source/components/npu_ta/CMakeLists.txt +++ b/source/hal/source/components/npu_ta/CMakeLists.txt @@ -1,5 +1,6 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its +# affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,16 +31,14 @@ project(${ETHOS_U_NPU_TA_COMPONENT} DESCRIPTION "Ethos-U NPU timing adapter initialization library" LANGUAGES C CXX ASM) +# # Checks +# ## Source generated Source path check if (NOT DEFINED SOURCE_GEN_DIR) set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/ta) endif() -# Base address definitions for the two timing adapters (platform should override these): -set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") -set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") - ## If a TA config file is provided, we generate a settings file if (DEFINED TA_CONFIG_FILE) include(${TA_CONFIG_FILE}) diff --git a/source/hal/source/components/npu_ta/ethosu_ta_init.c b/source/hal/source/components/npu_ta/ethosu_ta_init.c index 66fa9e7..1ef4ff5 100644 --- a/source/hal/source/components/npu_ta/ethosu_ta_init.c +++ b/source/hal/source/components/npu_ta/ethosu_ta_init.c @@ -48,7 +48,7 @@ int arm_ethosu_timing_adapter_init(void) } ta_set_all(&ta_0, &ta_0_settings); - info("TA0 values set\n"); + info("Configured TA0@0x%" PRIx32 "\n", TA0_BASE); #endif /* defined (TA0_BASE) */ #if defined(TA1_BASE) @@ -76,7 +76,7 @@ int arm_ethosu_timing_adapter_init(void) } ta_set_all(&ta_1, &ta_1_settings); - info("TA1 values set\n"); + info("Configured TA1@0x%" PRIx32 "\n", TA1_BASE); #endif /* defined (TA1_BASE) */ return 0; diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt index 5008f0b..4f77bdd 100644 --- a/source/hal/source/platform/mps3/CMakeLists.txt +++ b/source/hal/source/platform/mps3/CMakeLists.txt @@ -1,5 +1,6 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its +# affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,15 +37,23 @@ if (TARGET_SUBSYSTEM STREQUAL sse-300) set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate") set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)") set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address") - set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") set(ETHOS_U_IRQN "56" CACHE STRING "Ethos-U55 Interrupt") set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enable") set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable") - if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) - set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") - set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") - endif() + if (ETHOS_U_SEC_ENABLED) + set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") + set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") + endif() + else () + set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU timing adapter 0") + set(TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU timing adapter 1") + endif() + endif () endif() # Define target specific base addresses here (before adding the components) @@ -53,11 +62,17 @@ if (TARGET_SUBSYSTEM STREQUAL sse-310) set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate") set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)") set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address") - set(ETHOS_U_BASE_ADDR "0x50004000" CACHE STRING "Ethos-U NPU base address") + set(ETHOS_U_IRQN "16" CACHE STRING "Ethos-U55 Interrupt") set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enable") set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable") + if (ETHOS_U_SEC_ENABLED) + set(ETHOS_U_BASE_ADDR "0x50004000" CACHE STRING "Ethos-U NPU base address") + else () + set(ETHOS_U_BASE_ADDR "0x40004000" CACHE STRING "Ethos-U NPU base address") + endif () + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) message(FATAL_ERROR "Timing adapter support should be disabled for ${TARGET_SUBSYSTEM}") endif() diff --git a/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h b/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h index 85c7a8e..fd3ed15 100644 --- a/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h +++ b/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> - * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -65,10 +65,6 @@ #define CMSDK_UART2_BASE (0x49305000) /* UART 2 Base Address */ #define CMSDK_UART3_BASE (0x49306000) /* UART 3 Base Address Shield 0*/ -#define ETHOS_U_NPU_BASE (0x48102000) /* Ethos-U NPU base address*/ -#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */ -#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */ - #define CMSDK_UART4_BASE (0x49307000) /* UART 4 Base Address Shield 1*/ #define CMSDK_UART5_BASE (0x49308000) /* UART 5 Base Address */ /* #undef HDMI_AUDIO_BASE */ @@ -138,10 +134,6 @@ #define SEC_SMSC9220_BASE (0x51400000) /* Ethernet SMSC9220 Base Address */ #define SEC_USB_BASE (0x51500000) /* USB Base Address */ -#define SEC_ETHOS_U_NPU_BASE (0x58102000) /* Ethos-U NPU base address*/ -#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */ -#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */ - /* #undef SEC_USER_BASE */ #define SEC_QSPI_XIP_BASE (0x51800000) /* QSPI XIP config Base Address */ diff --git a/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h b/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h index eeaca69..3c7c031 100644 --- a/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h +++ b/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> - * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -65,10 +65,6 @@ #define CMSDK_UART2_BASE (0x49305000) /* UART 2 Base Address */ #define CMSDK_UART3_BASE (0x49306000) /* UART 3 Base Address Shield 0*/ -#define ETHOS_U_NPU_BASE (0x40004000) /* Ethos-U NPU base address*/ -#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */ -#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */ - #define CMSDK_UART4_BASE (0x49307000) /* UART 4 Base Address Shield 1*/ #define CMSDK_UART5_BASE (0x49308000) /* UART 5 Base Address */ /* #undef HDMI_AUDIO_BASE */ @@ -136,16 +132,9 @@ #define SEC_CLCD_CONFIG_BASE (0x5930A000) /* CLCD CONFIG Base Address */ #define SEC_RTC_BASE (0x5930B000) /* RTC Base address */ - - - #define SEC_SMSC9220_BASE (0x51400000) /* Ethernet SMSC91C111 Base Address */ #define SEC_USB_BASE (0x51500000) /* USB Base Address */ -#define SEC_ETHOS_U_NPU_BASE (0x50004000) /* Ethos-U NPU base address*/ -#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */ -#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */ - /* #undef SEC_USER_BASE */ #define SEC_QSPI_XIP_BASE (0x51800000) /* QSPI XIP config Base Address */ diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c index 73b388b..1890e3b 100644 --- a/source/hal/source/platform/mps3/source/platform_drivers.c +++ b/source/hal/source/platform/mps3/source/platform_drivers.c @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> - * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: Copyright 2022-2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -21,8 +21,6 @@ #include "uart_stdout.h" /* stdout over UART. */ #include "smm_mps3.h" /* Memory map for MPS3. */ -#include <string.h> /* For strncpy */ - #if defined(ARM_NPU) #include "ethosu_npu_init.h" @@ -30,14 +28,6 @@ #include "ethosu_ta_init.h" #endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */ -#if defined(ETHOS_U_BASE_ADDR) - #if (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) - #error "NPU component configured with incorrect NPU base address." - #endif /* (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE == ETHOS_U_BASE_ADDR) */ -#else - #error "ETHOS_U_BASE_ADDR should have been defined by the NPU component." -#endif /* defined(ETHOS_U_BASE_ADDR) */ - #endif /* ARM_NPU */ /** diff --git a/source/hal/source/platform/simple/include/peripheral_memmap.h b/source/hal/source/platform/simple/include/peripheral_memmap.h index 761fad9..e302e30 100644 --- a/source/hal/source/platform/simple/include/peripheral_memmap.h +++ b/source/hal/source/platform/simple/include/peripheral_memmap.h @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> - * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,23 +18,7 @@ #ifndef PERIPHERAL_MEMMAP_H #define PERIPHERAL_MEMMAP_H -#define DESIGN_NAME "Simple platform" - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -#define PL011_UART0_BASE (0x49303000) /* PL011 UART0 Base Address */ - -#define ETHOS_U_NPU_BASE (0x48102000) /* Ethos-U NPU base address*/ -#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */ -#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */ - -/******************************************************************************/ -/* Secure Peripheral memory map */ -/******************************************************************************/ - -#define SEC_ETHOS_U_NPU_BASE (0x58102000) /* Ethos-U NPU base address*/ -#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */ -#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */ +#define DESIGN_NAME "Simple platform" +#define PL011_UART0_BASE (0x49303000) /* PL011 UART0 Base Address */ #endif /* PERIPHERAL_MEMMAP_H */ diff --git a/source/hal/source/platform/simple/source/platform_drivers.c b/source/hal/source/platform/simple/source/platform_drivers.c index 914b1ac..af854d7 100644 --- a/source/hal/source/platform/simple/source/platform_drivers.c +++ b/source/hal/source/platform/simple/source/platform_drivers.c @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> - * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -30,14 +30,6 @@ #include "ethosu_ta_init.h" #endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */ -#if defined(ETHOS_U_BASE_ADDR) - #if (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) - #error "NPU component configured with incorrect NPU base address." - #endif /* (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE == ETHOS_U_BASE_ADDR) */ -#else - #error "ETHOS_U_BASE_ADDR should have been defined by the NPU component." -#endif /* defined(ETHOS_U_BASE_ADDR) */ - #endif /* ARM_NPU */ /* Platform name */ |