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| author | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2024-01-17 13:29:43 +0000 |
|---|---|---|
| committer | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2024-01-18 10:38:57 +0000 |
| commit | 5385a64979c0380b60c57c74878ccb5189012c87 (patch) | |
| tree | ba1879bb56501eae9334da379d3014ae99fd01fb /source/hal/source/platform/simple/include/peripheral_memmap.h | |
| parent | 001a8ff315dc766a206b05a3e00e831e3f972b0d (diff) | |
| download | ml-embedded-evaluation-kit-5385a64979c0380b60c57c74878ccb5189012c87.tar.gz | |
Cleanup: Timing adapter definitions
The NPU timing adapter base addresses had been defined in mutiple
places, making it difficult to determine which one is actually being
used. This patch cleans up unused definitions from memory-map header
files for different targets and the CMake template files.
The expectation is for component base addresses to be set by platform
specific CMake files that include/wrap the component directories.
Change-Id: Ic39794ffbdb872b4b0c900cbcec8e386bb32c4eb
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Diffstat (limited to 'source/hal/source/platform/simple/include/peripheral_memmap.h')
| -rw-r--r-- | source/hal/source/platform/simple/include/peripheral_memmap.h | 24 |
1 files changed, 4 insertions, 20 deletions
diff --git a/source/hal/source/platform/simple/include/peripheral_memmap.h b/source/hal/source/platform/simple/include/peripheral_memmap.h index 761fad9..e302e30 100644 --- a/source/hal/source/platform/simple/include/peripheral_memmap.h +++ b/source/hal/source/platform/simple/include/peripheral_memmap.h @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> - * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,23 +18,7 @@ #ifndef PERIPHERAL_MEMMAP_H #define PERIPHERAL_MEMMAP_H -#define DESIGN_NAME "Simple platform" - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -#define PL011_UART0_BASE (0x49303000) /* PL011 UART0 Base Address */ - -#define ETHOS_U_NPU_BASE (0x48102000) /* Ethos-U NPU base address*/ -#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */ -#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */ - -/******************************************************************************/ -/* Secure Peripheral memory map */ -/******************************************************************************/ - -#define SEC_ETHOS_U_NPU_BASE (0x58102000) /* Ethos-U NPU base address*/ -#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */ -#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */ +#define DESIGN_NAME "Simple platform" +#define PL011_UART0_BASE (0x49303000) /* PL011 UART0 Base Address */ #endif /* PERIPHERAL_MEMMAP_H */ |