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| author | Richard Burton <richard.burton@arm.com> | 2023-12-06 17:13:10 +0000 |
|---|---|---|
| committer | alex.tawse <alex.tawse@arm.com> | 2024-01-23 17:26:45 +0000 |
| commit | cefc7e1cacdd3028b46325b3a1f6c15416914b2f (patch) | |
| tree | d0353f7775d18a207d8a9fd352a3b716ea7b9773 /source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h | |
| parent | 001a8ff315dc766a206b05a3e00e831e3f972b0d (diff) | |
| download | ml-embedded-evaluation-kit-cefc7e1cacdd3028b46325b3a1f6c15416914b2f.tar.gz | |
MLECO-4503: Adding video VSI for object detectionexperimental/vsi
* Added Board support - Arm Corstone 300 and 310
* Added Python Scripts for Video VSI
* Added source files for Video VSI
* Add new usecase handler for OD use case
* Bumped resampy version to resolve issue with slowdown
Signed-off-by: Idriss Chaouch <idriss.chaouch@arm.com>
Signed-off-by: Richard Burton <richard.burton@arm.com>
Change-Id: Ie59ae955d4d85f672a49c63733052624542aec85
Diffstat (limited to 'source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h')
| -rw-r--r-- | source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h b/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h index 2085c6a..9fb7b9e 100644 --- a/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h +++ b/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -131,6 +131,14 @@ #define UARTRX5_IRQn (125) /* UART 5 RX Interrupt */ #define UARTTX5_IRQn (126) /* UART 5 TX Interrupt */ #define UART5_IRQn (127) /* UART 5 combined Interrupt */ +#define ARM_VSI0_IRQn (224) /* 224: VSI 0 */ +#define ARM_VSI1_IRQn (225) /* 225: VSI 1 */ +#define ARM_VSI2_IRQn (226) /* 226: VSI 2 */ +#define ARM_VSI3_IRQn (227) /* 227: VSI 3 */ +#define ARM_VSI4_IRQn (228) /* 228: VSI 4 */ +#define ARM_VSI5_IRQn (229) /* 229: VSI 5 */ +#define ARM_VSI6_IRQn (230) /* 230: VSI 6 */ +#define ARM_VSI7_IRQn (231) /* 231: VSI 7 */ /* #undef HDCLCD_IRQn */ #endif /* PERIPHERAL_IRQS_H */ |