diff options
author | alexander <alexander.efremov@arm.com> | 2022-02-10 16:15:54 +0000 |
---|---|---|
committer | alexander <alexander.efremov@arm.com> | 2022-02-10 18:04:42 +0000 |
commit | 31ae9f09bb3535975595e999fbc7baca889e46e8 (patch) | |
tree | 71f0cadc2620b9d18e474e5d40eda7b3d30a8ce4 /source/hal/platform/simple | |
parent | 3107aa2152de9be8317e62da1d0327bcad6552e2 (diff) | |
download | ml-embedded-evaluation-kit-31ae9f09bb3535975595e999fbc7baca889e46e8.tar.gz |
MLECO-2682: CMake and source refactoring.
MLECO-2930: logging macros were extracted from hal.h and used separately around the code.
MLECO-2931: arm_math lib introduced, cmsis-dsp removed from top level linkage.
MLECO-2915: platform related post-build steps.
Change-Id: Id718884e22f262a5c070ded3f3f5d4b048820147
Signed-off-by: alexander <alexander.efremov@arm.com>
Diffstat (limited to 'source/hal/platform/simple')
11 files changed, 729 insertions, 0 deletions
diff --git a/source/hal/platform/simple/CMakeLists.txt b/source/hal/platform/simple/CMakeLists.txt new file mode 100644 index 0000000..cd3a2bc --- /dev/null +++ b/source/hal/platform/simple/CMakeLists.txt @@ -0,0 +1,100 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2022 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +######################################################### +# A generic (simple) platform support library # +######################################################### + +cmake_minimum_required(VERSION 3.15.6) +set(PLATFORM_DRIVERS_TARGET platform-drivers) +project(${PLATFORM_DRIVERS_TARGET} + DESCRIPTION "Platform drivers library for a generic target" + LANGUAGES C CXX ASM) + +# 1. We should be cross-compiling (MPS3 taregt only runs Cortex-M targets) +if (NOT ${CMAKE_CROSSCOMPILING}) + message(FATAL_ERROR "No ${PLATFORM_DRIVERS_TARGET} support for this target.") +endif() + +# 2. Set the platform cmake descriptor file +if (NOT DEFINED PLATFORM_CMAKE_DESCRIPTOR_FILE) + set(PLATFORM_CMAKE_DESCRIPTOR_FILE + ${CMAKE_CURRENT_SOURCE_DIR}/cmake/subsystem-profiles/simple_platform.cmake) +endif() + +## Include the platform cmake descriptor file +include(${PLATFORM_CMAKE_DESCRIPTOR_FILE}) + +# 3. Generate sources: +if (NOT DEFINED SOURCE_GEN_DIR) + set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp) +endif() + +set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_memmap.h.template) +set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_irqs.h.template) +set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/mem_regions.h.template) + +configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h") +configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h") +configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h") + +# If a TA config file is provided, we generate a settings file +if (DEFINED TA_CONFIG_FILE) + include(${TA_CONFIG_FILE}) + set(TA_SETTINGS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/timing_adapter_settings.template) + configure_file("${TA_SETTINGS_TEMPLATE}" "${SOURCE_GEN_DIR}/timing_adapter_settings.h") +endif() + +# 4. Create static library +add_library(${PLATFORM_DRIVERS_TARGET} STATIC) + +## Include directories - public +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PUBLIC + include + ${SOURCE_GEN_DIR}) + +## Platform sources +target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + source/stubs_glcd.c + source/timer_simple_platform.c) + +## Platform component: uart +target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/../../components/uart_pl011/uart_pl011.c) +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/../../components/uart_pl011/include) + +## Compile defs +target_compile_definitions(${PLATFORM_DRIVERS_TARGET} + PUBLIC + ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ} + $<$<BOOL:TA_CONFIG_FILE>:TIMING_ADAPTER_AVAILABLE>) + +target_link_libraries(${PLATFORM_DRIVERS_TARGET} PUBLIC + cmsis_device + log) + +# 6 Display status: +message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR}) +message(STATUS "*******************************************************") +message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET}) +message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR}) +message(STATUS "*******************************************************") diff --git a/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake b/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake new file mode 100644 index 0000000..e6cfef3 --- /dev/null +++ b/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake @@ -0,0 +1,93 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2021 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +# CMake configuration file for peripheral memory map for simple platform. This is a stripped down +# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However, +# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of +# the CMSDK UART block used by the MPS3 FPGA and FVP implementations. +################################################################################################### +# Mem sizes # +################################################################################################### +set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB") +set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks") +set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB") +set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB") +set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB") +set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB") + +################################################################################################### +# Base addresses for memory regions # +################################################################################################### +set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address") +set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address") +set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address") +set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address") +set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address") +set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address") +set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address") +set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address") +set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address") +set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address") +set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address") +set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address") +set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address") + +set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address") +set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address") +set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address") +set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address") +set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address") +set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address") +set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address") +set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address") +set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address") +set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address") +set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address") +set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address") + +################################################################################################### +# Application specific config # +################################################################################################### + +# This parameter is based on the linker/scatter script for simple platform. Do not change this +# parameter in isolation. +set(DESIGN_NAME "Simple platform" CACHE STRING "Design name") + +# SRAM size reserved for activation buffers +math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL) + + +################################################################################################### +# Base addresses # +################################################################################################### +set(PL011_UART0_BASE "0x49303000" CACHE STRING "PL011 UART 0 Base Address") + +if (ETHOS_U_NPU_ENABLED) + set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address") + set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") + set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address") + set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") +endif () + +################################################################################################### +# IRQ numbers # +################################################################################################### +if (ETHOS_U_NPU_ENABLED) + set(EthosU_IRQn "56" CACHE STRING "Ethos-U NPU Interrupt") +endif () diff --git a/source/hal/platform/simple/cmake/templates/mem_regions.h.template b/source/hal/platform/simple/cmake/templates/mem_regions.h.template new file mode 100644 index 0000000..72978ce --- /dev/null +++ b/source/hal/platform/simple/cmake/templates/mem_regions.h.template @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef MEM_REGION_DEFS_H +#define MEM_REGION_DEFS_H + +#cmakedefine ITCM_SIZE (@ITCM_SIZE@) /* ITCM size */ +#cmakedefine DTCM_BLK_SIZE (@DTCM_BLK_SIZE@) /* DTCM size, 4 banks of this size available */ +#cmakedefine BRAM_SIZE (@BRAM_SIZE@) /* BRAM size */ +#cmakedefine ISRAM0_SIZE (@ISRAM0_SIZE@) /* ISRAM0 size */ +#cmakedefine ISRAM1_SIZE (@ISRAM1_SIZE@) /* ISRAM1 size */ +#cmakedefine QSPI_SRAM_SIZE (@QSPI_SRAM_SIZE@) /* QSPI Flash size */ +#cmakedefine DDR4_BLK_SIZE (@DDR4_BLK_SIZE@) /* DDR4 block size */ + +#cmakedefine ITCM_BASE_NS (@ITCM_BASE_NS@) /* Instruction TCM Non-Secure base address */ +#cmakedefine BRAM_BASE_NS (@BRAM_BASE_NS@) /* CODE SRAM Non-Secure base address */ +#cmakedefine DTCM0_BASE_NS (@DTCM0_BASE_NS@) /* Data TCM block 0 Non-Secure base address */ +#cmakedefine DTCM1_BASE_NS (@DTCM1_BASE_NS@) /* Data TCM block 1 Non-Secure base address */ +#cmakedefine DTCM2_BASE_NS (@DTCM2_BASE_NS@) /* Data TCM block 2 Non-Secure base address */ +#cmakedefine DTCM3_BASE_NS (@DTCM3_BASE_NS@) /* Data TCM block 3 Non-Secure base address */ +#cmakedefine ISRAM0_BASE_NS (@ISRAM0_BASE_NS@) /* Internal SRAM Area Non-Secure base address */ +#cmakedefine ISRAM1_BASE_NS (@ISRAM1_BASE_NS@) /* Internal SRAM Area Non-Secure base address */ +#cmakedefine QSPI_SRAM_BASE_NS (@QSPI_SRAM_BASE_NS@) /* QSPI SRAM Non-Secure base address */ +#cmakedefine DDR4_BLK0_BASE_NS (@DDR4_BLK0_BASE_NS@) /* DDR4 block 0 Non-Secure base address */ +#cmakedefine DDR4_BLK1_BASE_NS (@DDR4_BLK1_BASE_NS@) /* DDR4 block 1 Non-Secure base address */ +#cmakedefine DDR4_BLK2_BASE_NS (@DDR4_BLK2_BASE_NS@) /* DDR4 block 2 Non-Secure base address */ +#cmakedefine DDR4_BLK3_BASE_NS (@DDR4_BLK3_BASE_NS@) /* DDR4 block 3 Non-Secure base address */ + +#cmakedefine ITCM_BASE_S (@ITCM_BASE_S@) /* Instruction TCM Secure base address */ +#cmakedefine BRAM_BASE_S (@BRAM_BASE_S@) /* CODE SRAM Secure base address */ +#cmakedefine DTCM0_BASE_S (@DTCM0_BASE_S@) /* Data TCM block 0 Secure base address */ +#cmakedefine DTCM1_BASE_S (@DTCM1_BASE_S@) /* Data TCM block 1 Secure base address */ +#cmakedefine DTCM2_BASE_S (@DTCM2_BASE_S@) /* Data TCM block 2 Secure base address */ +#cmakedefine DTCM3_BASE_S (@DTCM3_BASE_S@) /* Data TCM block 3 Secure base address */ +#cmakedefine ISRAM0_BASE_S (@ISRAM0_BASE_S@) /* Internal SRAM Area Secure base address */ +#cmakedefine ISRAM1_BASE_S (@ISRAM1_BASE_S@) /* Internal SRAM Area Secure base address */ +#cmakedefine DDR4_BLK0_BASE_S (@DDR4_BLK0_BASE_S@) /* DDR4 block 0 Secure base address */ +#cmakedefine DDR4_BLK1_BASE_S (@DDR4_BLK1_BASE_S@) /* DDR4 block 1 Secure base address */ +#cmakedefine DDR4_BLK2_BASE_S (@DDR4_BLK2_BASE_S@) /* DDR4 block 2 Secure base address */ +#cmakedefine DDR4_BLK3_BASE_S (@DDR4_BLK3_BASE_S@) /* DDR4 block 3 Secure base address */ + +#endif /* MEM_REGION_DEFS_H */ diff --git a/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template b/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template new file mode 100644 index 0000000..8126cb4 --- /dev/null +++ b/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef PERIPHERAL_IRQS_H +#define PERIPHERAL_IRQS_H + +/******************************************************************************/ +/* Peripheral interrupt numbers */ +/******************************************************************************/ + +#cmakedefine EthosU_IRQn (@EthosU_IRQn@) /* Ethos-Uxx Interrupt */ + +#endif /* PERIPHERAL_IRQS_H */ diff --git a/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template b/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template new file mode 100644 index 0000000..2bfaafc --- /dev/null +++ b/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef PERIPHERAL_MEMMAP_H +#define PERIPHERAL_MEMMAP_H + +#cmakedefine DESIGN_NAME "@DESIGN_NAME@" + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#cmakedefine PL011_UART0_BASE (@PL011_UART0_BASE@) /* PL011 UART0 Base Address */ + +#cmakedefine ETHOS_U_NPU_BASE (@ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ +#cmakedefine ETHOS_U_NPU_TA0_BASE (@ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ +#cmakedefine ETHOS_U_NPU_TA1_BASE (@ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ + +/******************************************************************************/ +/* Secure Peripheral memory map */ +/******************************************************************************/ + +#cmakedefine SEC_ETHOS_U_NPU_BASE (@SEC_ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ +#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE (@SEC_ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ +#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE (@SEC_ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ + +#endif /* PERIPHERAL_MEMMAP_H */ diff --git a/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template b/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template new file mode 100644 index 0000000..d5e202a --- /dev/null +++ b/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef TIMING_ADAPTER_SETTINGS_H +#define TIMING_ADAPTER_SETTINGS_H + +#cmakedefine TA0_BASE (@TA0_BASE@) +#cmakedefine TA1_BASE (@TA1_BASE@) + +/* Timing adapter settings for AXI0 */ +#if defined(TA0_BASE) + +#define TA0_MAXR (@TA0_MAXR@) +#define TA0_MAXW (@TA0_MAXW@) +#define TA0_MAXRW (@TA0_MAXRW@) +#define TA0_RLATENCY (@TA0_RLATENCY@) +#define TA0_WLATENCY (@TA0_WLATENCY@) +#define TA0_PULSE_ON (@TA0_PULSE_ON@) +#define TA0_PULSE_OFF (@TA0_PULSE_OFF@) +#define TA0_BWCAP (@TA0_BWCAP@) +#define TA0_PERFCTRL (@TA0_PERFCTRL@) +#define TA0_PERFCNT (@TA0_PERFCNT@) +#define TA0_MODE (@TA0_MODE@) +#define TA0_HISTBIN (@TA0_HISTBIN@) +#define TA0_HISTCNT (@TA0_HISTCNT@) + +#endif /* defined(TA0_BASE) */ + +/* Timing adapter settings for AXI1 */ +#if defined(TA1_BASE) + +#define TA1_MAXR (@TA1_MAXR@) +#define TA1_MAXW (@TA1_MAXW@) +#define TA1_MAXRW (@TA1_MAXRW@) +#define TA1_RLATENCY (@TA1_RLATENCY@) +#define TA1_WLATENCY (@TA1_WLATENCY@) +#define TA1_PULSE_ON (@TA1_PULSE_ON@) +#define TA1_PULSE_OFF (@TA1_PULSE_OFF@) +#define TA1_BWCAP (@TA1_BWCAP@) +#define TA1_PERFCTRL (@TA1_PERFCTRL@) +#define TA1_PERFCNT (@TA1_PERFCNT@) +#define TA1_MODE (@TA1_MODE@) +#define TA1_HISTBIN (@TA1_HISTBIN@) +#define TA1_HISTCNT (@TA1_HISTCNT@) + +#endif /* defined(TA1_BASE) */ + +#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file diff --git a/source/hal/platform/simple/include/platform_drivers.h b/source/hal/platform/simple/include/platform_drivers.h new file mode 100644 index 0000000..0fb092e --- /dev/null +++ b/source/hal/platform/simple/include/platform_drivers.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PLATFORM_DRIVER_H +#define PLATFORM_DRIVER_H + +#include "log_macros.h" /* Logging related helpers. */ + +/* Platform components */ +#include "uart_stdout.h" /* stdout over UART. */ +#include "stubs/glcd.h" /* LCD stubs to support use cases that use LCD */ +#include "timer_simple_platform.h" /* timer implementation */ + +#include "cmsis.h" /* CPU device specific header file */ +#include "peripheral_memmap.h" /* peripheral memory map definitions */ +#include "peripheral_irqs.h" /* IRQ numbers for the platform */ + +#endif /* PLATFORM_DRIVER_H */ diff --git a/source/hal/platform/simple/include/stubs/glcd.h b/source/hal/platform/simple/include/stubs/glcd.h new file mode 100644 index 0000000..5915f7d --- /dev/null +++ b/source/hal/platform/simple/include/stubs/glcd.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef STUBS_SIMPLE_PLATFORM_H +#define STUBS_SIMPLE_PLATFORM_H + +/****************************************************************************/ +/* Definitions and stub functions for modules currently */ +/* unavailable on this target platform */ +/****************************************************************************/ +#define GLCD_WIDTH 320 +#define GLCD_HEIGHT 240 +#define Black 0x0000 /* 0, 0, 0 */ +#define White 0xFFFF /* 255, 255, 255 */ + +/************************ GLCD related functions ****************************/ +/** + * @brief Initialize the Himax LCD with HX8347-D LCD Controller + */ +void GLCD_Initialize(void); + +/** + * @brief Display graphical bitmap image at position x horizontally and y + * vertically. This function is optimized for 16 bits per pixel + * format, it has to be adapted for any other format. + * @param[in] x horizontal position. + * @param[in] y vertical position. + * @param[in] w width of bitmap. + * @param[in] h height of bitmap. + * @param[in] bitmap address at which the bitmap data resides. + */ +void GLCD_Bitmap(unsigned int x, unsigned int y, + unsigned int w, unsigned int h, + unsigned short *bitmap); + +/** + * @brief Displays an 8 bit image, conversion to the LCD's + * 16 bit codec is done on the fly. + * @param[in] data pointer to the full sized image data. + * @param[in] width image width. + * @param[in] height image height. + * @param[in] channels number of channels in the image. + * @param[in] pos_x start x position for the LCD. + * @param[in] pos_y start y position for the LCD. + * @param[in] downsample_factor factor by which the image + * is downsampled by. + */ +void GLCD_Image(void *data, const unsigned int width, + const unsigned int height, const unsigned int channels, + const unsigned int pos_x, const unsigned int pos_y, + const unsigned int downsample_factor); + +/** + * @brief Clear display + * @param[in] color display clearing color + */ +void GLCD_Clear(unsigned short color); + +/** + * @brief Set foreground color + * @param[in] color foreground color + */ +void GLCD_SetTextColor(unsigned short color); + +/** + * @brief Display character on given line + * @param[in] ln line number + * @param[in] col column number + * @param[in] fi font index (0 = 9x15) + * @param[in] c ASCII character + */ +void GLCD_DisplayChar(unsigned int ln, unsigned int col, + unsigned char fi, unsigned char c); + +/** + * @brief Display string on given line + * @param[in] ln line number + * @param[in] col column number + * @param[in] fi font index (0 = 9x15) + * @param[in] s pointer to string + */ +void GLCD_DisplayString(unsigned int ln, unsigned int col, + unsigned char fi, char *s); + +/** + * @brief Draw box filled with color + * @param[in] x horizontal position + * @param[in] y: vertical position + * @param[in] w: window width in pixels + * @param[in] h: window height in pixels + * @param[in] color box color + */ +void GLCD_Box(unsigned int x, unsigned int y, + unsigned int w, unsigned int h, + unsigned short color); + +#endif /* STUBS_SIMPLE_PLATFORM_H */ diff --git a/source/hal/platform/simple/include/timer_simple_platform.h b/source/hal/platform/simple/include/timer_simple_platform.h new file mode 100644 index 0000000..03d8245 --- /dev/null +++ b/source/hal/platform/simple/include/timer_simple_platform.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef TIMER_SIMPLE_PLATFORM_H +#define TIMER_SIMPLE_PLATFORM_H +#include <stdint.h> + +/* Container for timestamp for simple platform. */ +typedef struct _generic_time_counter { + uint64_t counter_systick; +} base_time_counter; + +/** + * @brief Resets the counters. + */ +void timer_reset(void); + +/** + * @brief Gets the current counter values. + * @returns counter struct. + **/ +base_time_counter get_time_counter(void); + +/** + * @brief Gets the cycle counts elapsed between start and end. + * @return difference in counter values as 32 bit unsigned integer. + */ +uint64_t get_cycle_count_diff(base_time_counter *start, base_time_counter *end); + +/** + * @brief Enables or triggers cycle counting mechanism, if required + * by the platform. + */ +void start_cycle_counter(void); + +/** + * @brief Stops cycle counting mechanism, if required by the platform. + */ +void stop_cycle_counter(void); + +#endif /* TIMER_SIMPLE_PLATFORM_H */ diff --git a/source/hal/platform/simple/source/stubs_glcd.c b/source/hal/platform/simple/source/stubs_glcd.c new file mode 100644 index 0000000..6b60dcd --- /dev/null +++ b/source/hal/platform/simple/source/stubs_glcd.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "stubs/glcd.h" +#include "log_macros.h" + +#include <inttypes.h> + +void GLCD_Initialize(void) {} + +void GLCD_Bitmap(unsigned int x, unsigned int y, + unsigned int w, unsigned int h, unsigned short *bitmap) +{ + UNUSED(x); + UNUSED(y); + UNUSED(w); + UNUSED(h); + UNUSED(bitmap); +} + +void GLCD_Image(void *data, const unsigned int width, const unsigned int height, + const unsigned int channels, const unsigned int pos_x, + const unsigned int pos_y, const unsigned int downsample_factor) +{ + UNUSED(data); + UNUSED(pos_x); + UNUSED(pos_y); + UNUSED(width); + UNUSED(height); + UNUSED(channels); + UNUSED(downsample_factor); + debug("image display: (x, y, w, h) = " + "(%" PRIu32 ", %" PRIu32 ", %" PRIu32 ", %" PRIu32 ")\n", + pos_x, pos_y, width, height); + debug("image display: channels = %" PRIu32 ", downsample factor = %" PRIu32 "\n", + channels, downsample_factor); +} + +void GLCD_Clear(unsigned short color) +{ + UNUSED(color); +} + +void GLCD_SetTextColor(unsigned short color) +{ + UNUSED(color); +} + +void GLCD_DisplayChar (unsigned int ln, unsigned int col, unsigned char fi, + unsigned char c) +{ + UNUSED(ln); + UNUSED(col); + UNUSED(fi); + UNUSED(c); +} + +void GLCD_DisplayString(unsigned int ln, unsigned int col, unsigned char fi, + char *s) +{ + UNUSED(ln); + UNUSED(col); + UNUSED(fi); + UNUSED(s); + debug("text display: %s\n", s); +} + +void GLCD_Box(unsigned int x, unsigned int y, unsigned int w, unsigned int h, + unsigned short color) +{ + UNUSED(x); + UNUSED(y); + UNUSED(w); + UNUSED(h); + UNUSED(color); +} diff --git a/source/hal/platform/simple/source/timer_simple_platform.c b/source/hal/platform/simple/source/timer_simple_platform.c new file mode 100644 index 0000000..4bcd07b --- /dev/null +++ b/source/hal/platform/simple/source/timer_simple_platform.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "timer_simple_platform.h" + +#include "irqs.h" +#include "log_macros.h" + +#include <inttypes.h> + +base_time_counter get_time_counter(void) +{ + base_time_counter t = { + .counter_systick = Get_SysTick_Cycle_Count() + }; + debug("counter_systick: %" PRIu64 "\n", t.counter_systick); + return t; +} + +void timer_reset(void) +{ + if (0 != Init_SysTick()) { + printf_err("Failed to initialise system tick config\n"); + } + debug("system tick config ready\n"); +} + +uint64_t get_cycle_count_diff(base_time_counter *start, + base_time_counter *end) +{ + if (start->counter_systick > end->counter_systick) { + warn("start > end; counter might have overflown\n"); + } + return end->counter_systick - start->counter_systick; +} + +void start_cycle_counter(void) +{ + /* Add any custom requirement for this platform here */ +} + +void stop_cycle_counter(void) +{ + /* Add any custom requirement for this platform here */ +} |