MLECO-2919: Restructuring to standardise HAL APIs

* LCD module component created (removed from individual
  platform packs).

* retarget.c moved out into its own component that wraps
  the uart module. It also have the native stub for
  GetLine => paved the way for removing data_acq module
  from profiles.

* shortened names for components' dir for npu and ta

* remove peripheral_memmap and peripheral_irqs headers
  from platform_drivers.h. There should be no need for
  these to be included in the top level now. These should
  be private headers.

* cmsis_device moved in as a component.

* Pyenv created by set_up_default_resource.py will also
  install packages that CMake's source generator needs.

TODO's:

* Remove timer from profiles (MLECO-3096)

Change-Id: I9d6ea2f4f291788f40a16ed507019563c8d7f205

5 files changed, 0 insertions, 286 deletions

diff --git a/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake b/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake
deleted file mode 100644
index e6cfef3..0000000
--- a/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake
+++ /dev/null
@@ -1,93 +0,0 @@
-#----------------------------------------------------------------------------
-#  Copyright (c) 2021 Arm Limited. All rights reserved.
-#  SPDX-License-Identifier: Apache-2.0
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#----------------------------------------------------------------------------
-
-# CMake configuration file for peripheral memory map for simple platform. This is a stripped down
-# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However,
-# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of
-# the CMSDK UART block used by the MPS3 FPGA and FVP implementations.
-###################################################################################################
-#                                         Mem sizes                                               #
-###################################################################################################
-set(ITCM_SIZE             "0x00080000" CACHE STRING "ITCM size:       512 kiB")
-set(DTCM_BLK_SIZE         "0x00020000" CACHE STRING "DTCM size:       128 kiB, 4 banks")
-set(BRAM_SIZE             "0x00100000" CACHE STRING "BRAM size:         1 MiB")
-set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
-set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
-set(DDR4_BLK_SIZE         "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
-
-###################################################################################################
-#                                Base addresses for memory regions                                #
-###################################################################################################
-set(ITCM_BASE_NS          "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
-set(BRAM_BASE_NS          "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
-set(DTCM0_BASE_NS         "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
-set(DTCM1_BASE_NS         "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
-set(DTCM2_BASE_NS         "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
-set(DTCM3_BASE_NS         "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
-set(ISRAM0_BASE_NS        "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(ISRAM1_BASE_NS        "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(QSPI_SRAM_BASE_NS     "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
-set(DDR4_BLK0_BASE_NS     "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
-set(DDR4_BLK1_BASE_NS     "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
-set(DDR4_BLK2_BASE_NS     "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
-set(DDR4_BLK3_BASE_NS     "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
-
-set(ITCM_BASE_S           "0x10000000" CACHE STRING "Instruction TCM Secure base address")
-set(BRAM_BASE_S           "0x11000000" CACHE STRING "CODE SRAM Secure base address")
-set(DTCM0_BASE_S          "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
-set(DTCM1_BASE_S          "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
-set(DTCM2_BASE_S          "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
-set(DTCM3_BASE_S          "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
-set(ISRAM0_BASE_S         "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
-set(ISRAM1_BASE_S         "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
-set(DDR4_BLK0_BASE_S      "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
-set(DDR4_BLK1_BASE_S      "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
-set(DDR4_BLK2_BASE_S      "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
-set(DDR4_BLK3_BASE_S      "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
-
-###################################################################################################
-#                              Application specific config                                        #
-###################################################################################################
-
-# This parameter is based on the linker/scatter script for simple platform. Do not change this
-# parameter in isolation.
-set(DESIGN_NAME            "Simple platform" CACHE STRING "Design name")
-
-# SRAM size reserved for activation buffers
-math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-
-
-###################################################################################################
-#                                         Base addresses                                          #
-###################################################################################################
-set(PL011_UART0_BASE            "0x49303000" CACHE STRING "PL011 UART 0 Base Address")
-
-if (ETHOS_U_NPU_ENABLED)
-    set(ETHOS_U_NPU_BASE          "0x48102000" CACHE STRING "Ethos-U NPU base address")
-    set(ETHOS_U_NPU_TA0_BASE      "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(ETHOS_U_NPU_TA1_BASE      "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-    set(SEC_ETHOS_U_NPU_BASE      "0x58102000" CACHE STRING "Ethos-U NPU base address")
-    set(SEC_ETHOS_U_NPU_TA0_BASE  "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(SEC_ETHOS_U_NPU_TA1_BASE  "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-endif ()
-
-###################################################################################################
-#                                           IRQ numbers                                           #
-###################################################################################################
-if (ETHOS_U_NPU_ENABLED)
-    set(EthosU_IRQn             "56"         CACHE STRING "Ethos-U NPU Interrupt")
-endif ()
diff --git a/source/hal/platform/simple/cmake/templates/mem_regions.h.template b/source/hal/platform/simple/cmake/templates/mem_regions.h.template
deleted file mode 100644
index 72978ce..0000000
--- a/source/hal/platform/simple/cmake/templates/mem_regions.h.template
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef MEM_REGION_DEFS_H
-#define MEM_REGION_DEFS_H
-
-#cmakedefine ITCM_SIZE             (@ITCM_SIZE@)     /* ITCM size */
-#cmakedefine DTCM_BLK_SIZE         (@DTCM_BLK_SIZE@)     /* DTCM size, 4 banks of this size available */
-#cmakedefine BRAM_SIZE             (@BRAM_SIZE@)     /* BRAM size */
-#cmakedefine ISRAM0_SIZE           (@ISRAM0_SIZE@)     /* ISRAM0 size */
-#cmakedefine ISRAM1_SIZE           (@ISRAM1_SIZE@)     /* ISRAM1 size */
-#cmakedefine QSPI_SRAM_SIZE        (@QSPI_SRAM_SIZE@)     /* QSPI Flash size */
-#cmakedefine DDR4_BLK_SIZE         (@DDR4_BLK_SIZE@)     /* DDR4 block size */
-
-#cmakedefine ITCM_BASE_NS          (@ITCM_BASE_NS@)     /* Instruction TCM Non-Secure base address */
-#cmakedefine BRAM_BASE_NS          (@BRAM_BASE_NS@)     /* CODE SRAM Non-Secure base address */
-#cmakedefine DTCM0_BASE_NS         (@DTCM0_BASE_NS@)     /* Data TCM block 0 Non-Secure base address */
-#cmakedefine DTCM1_BASE_NS         (@DTCM1_BASE_NS@)     /* Data TCM block 1 Non-Secure base address */
-#cmakedefine DTCM2_BASE_NS         (@DTCM2_BASE_NS@)     /* Data TCM block 2 Non-Secure base address */
-#cmakedefine DTCM3_BASE_NS         (@DTCM3_BASE_NS@)     /* Data TCM block 3 Non-Secure base address */
-#cmakedefine ISRAM0_BASE_NS        (@ISRAM0_BASE_NS@)     /* Internal SRAM Area Non-Secure base address */
-#cmakedefine ISRAM1_BASE_NS        (@ISRAM1_BASE_NS@)     /* Internal SRAM Area Non-Secure base address */
-#cmakedefine QSPI_SRAM_BASE_NS     (@QSPI_SRAM_BASE_NS@)     /* QSPI SRAM Non-Secure base address */
-#cmakedefine DDR4_BLK0_BASE_NS     (@DDR4_BLK0_BASE_NS@)     /* DDR4 block 0 Non-Secure base address */
-#cmakedefine DDR4_BLK1_BASE_NS     (@DDR4_BLK1_BASE_NS@)     /* DDR4 block 1 Non-Secure base address */
-#cmakedefine DDR4_BLK2_BASE_NS     (@DDR4_BLK2_BASE_NS@)     /* DDR4 block 2 Non-Secure base address */
-#cmakedefine DDR4_BLK3_BASE_NS     (@DDR4_BLK3_BASE_NS@)     /* DDR4 block 3 Non-Secure base address */
-
-#cmakedefine ITCM_BASE_S           (@ITCM_BASE_S@)     /* Instruction TCM Secure base address */
-#cmakedefine BRAM_BASE_S           (@BRAM_BASE_S@)     /* CODE SRAM Secure base address */
-#cmakedefine DTCM0_BASE_S          (@DTCM0_BASE_S@)     /* Data TCM block 0 Secure base address */
-#cmakedefine DTCM1_BASE_S          (@DTCM1_BASE_S@)     /* Data TCM block 1 Secure base address */
-#cmakedefine DTCM2_BASE_S          (@DTCM2_BASE_S@)     /* Data TCM block 2 Secure base address */
-#cmakedefine DTCM3_BASE_S          (@DTCM3_BASE_S@)     /* Data TCM block 3 Secure base address */
-#cmakedefine ISRAM0_BASE_S         (@ISRAM0_BASE_S@)     /* Internal SRAM Area Secure base address */
-#cmakedefine ISRAM1_BASE_S         (@ISRAM1_BASE_S@)     /* Internal SRAM Area Secure base address */
-#cmakedefine DDR4_BLK0_BASE_S      (@DDR4_BLK0_BASE_S@)     /* DDR4 block 0 Secure base address */
-#cmakedefine DDR4_BLK1_BASE_S      (@DDR4_BLK1_BASE_S@)     /* DDR4 block 1 Secure base address */
-#cmakedefine DDR4_BLK2_BASE_S      (@DDR4_BLK2_BASE_S@)     /* DDR4 block 2 Secure base address */
-#cmakedefine DDR4_BLK3_BASE_S      (@DDR4_BLK3_BASE_S@)     /* DDR4 block 3 Secure base address */
-
-#endif /*  MEM_REGION_DEFS_H  */
diff --git a/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template b/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template
deleted file mode 100644
index 8126cb4..0000000
--- a/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef PERIPHERAL_IRQS_H
-#define PERIPHERAL_IRQS_H
-
-/******************************************************************************/
-/*                    Peripheral interrupt numbers                            */
-/******************************************************************************/
-
-#cmakedefine EthosU_IRQn                (@EthosU_IRQn@)   /* Ethos-Uxx Interrupt */
-
-#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template b/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template
deleted file mode 100644
index 2bfaafc..0000000
--- a/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef PERIPHERAL_MEMMAP_H
-#define PERIPHERAL_MEMMAP_H
-
-#cmakedefine DESIGN_NAME              "@DESIGN_NAME@"
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-#cmakedefine PL011_UART0_BASE         (@PL011_UART0_BASE@)       /* PL011 UART0 Base Address */
-
-#cmakedefine ETHOS_U_NPU_BASE           (@ETHOS_U_NPU_BASE@)    /* Ethos-U NPU base address*/
-#cmakedefine ETHOS_U_NPU_TA0_BASE       (@ETHOS_U_NPU_TA0_BASE@)    /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine ETHOS_U_NPU_TA1_BASE       (@ETHOS_U_NPU_TA1_BASE@)    /* Ethos-U NPU's timing adapter 1 base address */
-
-/******************************************************************************/
-/*                      Secure Peripheral memory map                          */
-/******************************************************************************/
-
-#cmakedefine SEC_ETHOS_U_NPU_BASE       (@SEC_ETHOS_U_NPU_BASE@)   /* Ethos-U NPU base address*/
-#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE   (@SEC_ETHOS_U_NPU_TA0_BASE@)   /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE   (@SEC_ETHOS_U_NPU_TA1_BASE@)   /* Ethos-U NPU's timing adapter 1 base address */
-
-#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template b/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template
deleted file mode 100644
index d5e202a..0000000
--- a/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef TIMING_ADAPTER_SETTINGS_H
-#define TIMING_ADAPTER_SETTINGS_H
-
-#cmakedefine TA0_BASE       (@TA0_BASE@)
-#cmakedefine TA1_BASE       (@TA1_BASE@)
-
-/* Timing adapter settings for AXI0 */
-#if defined(TA0_BASE)
-
-#define TA0_MAXR           (@TA0_MAXR@)
-#define TA0_MAXW           (@TA0_MAXW@)
-#define TA0_MAXRW          (@TA0_MAXRW@)
-#define TA0_RLATENCY       (@TA0_RLATENCY@)
-#define TA0_WLATENCY       (@TA0_WLATENCY@)
-#define TA0_PULSE_ON       (@TA0_PULSE_ON@)
-#define TA0_PULSE_OFF      (@TA0_PULSE_OFF@)
-#define TA0_BWCAP          (@TA0_BWCAP@)
-#define TA0_PERFCTRL       (@TA0_PERFCTRL@)
-#define TA0_PERFCNT        (@TA0_PERFCNT@)
-#define TA0_MODE           (@TA0_MODE@)
-#define TA0_HISTBIN        (@TA0_HISTBIN@)
-#define TA0_HISTCNT        (@TA0_HISTCNT@)
-
-#endif /* defined(TA0_BASE) */
-
-/* Timing adapter settings for AXI1 */
-#if defined(TA1_BASE)
-
-#define TA1_MAXR           (@TA1_MAXR@)
-#define TA1_MAXW           (@TA1_MAXW@)
-#define TA1_MAXRW          (@TA1_MAXRW@)
-#define TA1_RLATENCY       (@TA1_RLATENCY@)
-#define TA1_WLATENCY       (@TA1_WLATENCY@)
-#define TA1_PULSE_ON       (@TA1_PULSE_ON@)
-#define TA1_PULSE_OFF      (@TA1_PULSE_OFF@)
-#define TA1_BWCAP          (@TA1_BWCAP@)
-#define TA1_PERFCTRL       (@TA1_PERFCTRL@)
-#define TA1_PERFCNT        (@TA1_PERFCNT@)
-#define TA1_MODE           (@TA1_MODE@)
-#define TA1_HISTBIN        (@TA1_HISTBIN@)
-#define TA1_HISTCNT        (@TA1_HISTCNT@)
-
-#endif /* defined(TA1_BASE) */
-
-#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file