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| author | Isabella Gottardi <isabella.gottardi@arm.com> | 2021-09-16 17:54:35 +0100 |
|---|---|---|
| committer | Isabella Gottardi <isabella.gottardi@arm.com> | 2021-10-05 14:00:47 +0000 |
| commit | 118f73e0396fe66ee5cc3c0daec0882c7160a7cb (patch) | |
| tree | fa604ebef4a221844c294b76598c259a12feb61d /source/application/tensorflow-lite-micro | |
| parent | 5c0ce54aaf276a13ac30902e8181faa662289b33 (diff) | |
| download | ml-embedded-evaluation-kit-118f73e0396fe66ee5cc3c0daec0882c7160a7cb.tar.gz | |
MLECO-2395: Allow users to select Ethos-U memory mode
Change-Id: Icf09410f12072e8d7850dd1e540c3243af24ed09
Diffstat (limited to 'source/application/tensorflow-lite-micro')
| -rw-r--r-- | source/application/tensorflow-lite-micro/include/BufAttributes.hpp | 32 |
1 files changed, 12 insertions, 20 deletions
diff --git a/source/application/tensorflow-lite-micro/include/BufAttributes.hpp b/source/application/tensorflow-lite-micro/include/BufAttributes.hpp index 126172b..a3b5890 100644 --- a/source/application/tensorflow-lite-micro/include/BufAttributes.hpp +++ b/source/application/tensorflow-lite-micro/include/BufAttributes.hpp @@ -18,6 +18,17 @@ #ifndef BUF_ATTRIBUTES_HPP #define BUF_ATTRIBUTES_HPP +#if defined(ARM_NPU) + /* When Arm NPU is defined, we use the config set by NPU mem parameters */ + #include "ethosu_mem_config.h" + #define BYTE_ALIGNMENT ETHOS_U_MEM_BYTE_ALIGNMENT +#else /* defined(ARM_NPU) */ + /* otherwise, we use the default ones here. */ + #define ACTIVATION_BUF_SECTION section(".bss.NoInit.activation_buf_sram") + #define ACTIVATION_BUF_SECTION_NAME ("SRAM") + #define BYTE_ALIGNMENT 16 +#endif /* defined(ARM_NPU) */ + #ifdef __has_attribute #define HAVE_ATTRIBUTE(x) __has_attribute(x) #else /* __has_attribute */ @@ -27,9 +38,8 @@ #if HAVE_ATTRIBUTE(aligned) || (defined(__GNUC__) && !defined(__clang__)) /* We want all buffers/sections to be aligned to 16 byte. */ -#define ALIGNMENT_REQ aligned(16) +#define ALIGNMENT_REQ aligned(BYTE_ALIGNMENT) -/* Model data section name. */ #define MODEL_SECTION section("nn_model") /* Label section name */ @@ -45,24 +55,6 @@ #define ACTIVATION_BUF_SRAM_SZ 0x00000000 #endif /* ACTIVATION_BUF_SRAM_SZ */ -/** - * Activation buffer aka tensor arena section name - * We have to place the tensor arena in different region based on its size. - * If it fits in SRAM, we place it there, and also mark it by giving it a - * different section name. The scatter file places the ZI data in DDR and - * the uninitialised region in the SRAM. - **/ -#define ACTIVATION_BUF_SECTION_SRAM section(".bss.NoInit.activation_buf") -#define ACTIVATION_BUF_SECTION_DRAM section("activation_buf") - -#if ACTIVATION_BUF_SZ > ACTIVATION_BUF_SRAM_SZ /* Will buffer not fit in SRAM? */ - #define ACTIVATION_BUF_SECTION ACTIVATION_BUF_SECTION_DRAM - #define ACTIVATION_BUF_SECTION_NAME ("DDR") -#else /* ACTIVATION_BUF_SZ > 0x00200000 */ - #define ACTIVATION_BUF_SECTION ACTIVATION_BUF_SECTION_SRAM - #define ACTIVATION_BUF_SECTION_NAME ("SRAM") -#endif /* ACTIVATION_BUF_SZ > 0x00200000 */ - /* IFM section name. */ #define IFM_BUF_SECTION section("ifm") |