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| author | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2021-05-19 10:30:06 +0100 |
|---|---|---|
| committer | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2021-05-19 10:47:59 +0100 |
| commit | 659fcd951ac18d1ee7737a6ddf6a3ec162c73ca5 (patch) | |
| tree | 091232857b7ce8a52a7656424db4e4536b45cc7b /source/application/hal/platforms/bare-metal/timer/baremetal_timer.c | |
| parent | a3d87702b743e4e2d2ef08f0210445b01a86c87c (diff) | |
| download | ml-embedded-evaluation-kit-659fcd951ac18d1ee7737a6ddf6a3ec162c73ca5.tar.gz | |
MLECO-1933, MLECO-1914, MLECO-1885: Update to 21.05-rc2 components
Core driver and sofware dependencies updated to latest release
candidate revisions. Note: TensorFlow Lite Micro has not been
updated.
Also, gcc warnings for simple_platform target and ad use case have
been fixed.
Change-Id: I455b421f34375a719a941e6e220fe292a57613f5
Diffstat (limited to 'source/application/hal/platforms/bare-metal/timer/baremetal_timer.c')
| -rw-r--r-- | source/application/hal/platforms/bare-metal/timer/baremetal_timer.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c b/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c index cd17a60..00028bd 100644 --- a/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c +++ b/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c @@ -260,7 +260,7 @@ static uint64_t bm_get_npu_axi0_read_cycle_diff(time_counter *st, time_counter * printf_err("EthosU PMU axi0 read counter overflow.\n"); return 0; } - return (uint64_t)(end->npu_axi0_read_ccnt - st->npu_axi0_read_ccnt); + return (uint64_t)(end->npu_axi0_read_beats - st->npu_axi0_read_beats); } static uint64_t bm_get_npu_axi0_write_cycle_diff(time_counter *st, time_counter *end) @@ -269,7 +269,7 @@ static uint64_t bm_get_npu_axi0_write_cycle_diff(time_counter *st, time_counter printf_err("EthosU PMU axi0 write counter overflow.\n"); return 0; } - return (uint64_t)(end->npu_axi0_write_ccnt - st->npu_axi0_write_ccnt); + return (uint64_t)(end->npu_axi0_write_beats - st->npu_axi0_write_beats); } static uint64_t bm_get_npu_axi1_read_cycle_diff(time_counter *st, time_counter *end) @@ -278,7 +278,7 @@ static uint64_t bm_get_npu_axi1_read_cycle_diff(time_counter *st, time_counter * printf_err("EthosU PMU axi1 read counter overflow.\n"); return 0; } - return (uint64_t)(end->npu_axi1_read_ccnt - st->npu_axi1_read_ccnt); + return (uint64_t)(end->npu_axi1_read_beats - st->npu_axi1_read_beats); } #endif /* defined (ARM_NPU) */ @@ -300,9 +300,9 @@ static time_counter bm_get_time_counter(void) #if defined (ARM_NPU) .npu_total_ccnt = ETHOSU_PMU_Get_CCNTR(), .npu_idle_ccnt = ETHOSU_PMU_Get_EVCNTR(0), - .npu_axi0_read_ccnt = ETHOSU_PMU_Get_EVCNTR(1), - .npu_axi0_write_ccnt = ETHOSU_PMU_Get_EVCNTR(2), - .npu_axi1_read_ccnt = ETHOSU_PMU_Get_EVCNTR(3) + .npu_axi0_read_beats = ETHOSU_PMU_Get_EVCNTR(1), + .npu_axi0_write_beats = ETHOSU_PMU_Get_EVCNTR(2), + .npu_axi1_read_beats = ETHOSU_PMU_Get_EVCNTR(3) #endif /* defined (ARM_NPU) */ }; @@ -310,14 +310,14 @@ static time_counter bm_get_time_counter(void) #if defined (ARM_NPU) debug("NPU total cc: %" PRIu64 "; NPU idle cc: %" PRIu32 - "; NPU axi0 read cc: %" PRIu32 - "; NPU axi0 write cc: %" PRIu32 - "; NPU axi1 read cc: %" PRIu32 "\n", + "; NPU axi0 read beats: %" PRIu32 + "; NPU axi0 write beats: %" PRIu32 + "; NPU axi1 read beats: %" PRIu32 "\n", t.npu_total_ccnt, t.npu_idle_ccnt, - t.npu_axi0_read_ccnt, - t.npu_axi0_write_ccnt, - t.npu_axi1_read_ccnt); + t.npu_axi0_read_beats, + t.npu_axi0_write_beats, + t.npu_axi1_read_beats); #endif /* defined (ARM_NPU) */ return t; |