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| author | Isabella Gottardi <isabella.gottardi@arm.com> | 2021-09-16 17:54:35 +0100 |
|---|---|---|
| committer | Isabella Gottardi <isabella.gottardi@arm.com> | 2021-10-05 14:00:47 +0000 |
| commit | 118f73e0396fe66ee5cc3c0daec0882c7160a7cb (patch) | |
| tree | fa604ebef4a221844c294b76598c259a12feb61d /source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld | |
| parent | 5c0ce54aaf276a13ac30902e8181faa662289b33 (diff) | |
| download | ml-embedded-evaluation-kit-118f73e0396fe66ee5cc3c0daec0882c7160a7cb.tar.gz | |
MLECO-2395: Allow users to select Ethos-U memory mode
Change-Id: Icf09410f12072e8d7850dd1e540c3243af24ed09
Diffstat (limited to 'source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld')
| -rw-r--r-- | source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld index ceaff7d..e5b6bd9 100644 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld @@ -137,7 +137,11 @@ SECTIONS .sram : { . = ALIGN(16); - *(.bss.NoInit.activation_buf) + /* Cache area (if used) */ + *(.bss.NoInit.ethos_u_cache) + . = ALIGN (16); + /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */ + *(.bss.NoInit.activation_buf_sram) . = ALIGN(16); } > SRAM AT > SRAM @@ -170,13 +174,17 @@ SECTIONS /* __attribute__((aligned(16))) is not handled by the CMSIS startup code. * Force the alignment here as a workaround */ . = ALIGN(16); + /* nn model's baked in input matrices */ *(ifm) . = ALIGN(16); + /* nn model's default space */ *(nn_model) . = ALIGN (16); + /* labels */ *(labels) . = ALIGN (16); - *(activation_buf) + /* activation buffers a.k.a tensor arena when memory mode dedicated sram */ + *(activation_buf_dram) . = ALIGN (16); } > DDR AT > DDR |