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| author | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2021-10-04 12:20:33 +0100 |
|---|---|---|
| committer | Isabella Gottardi <isabella.gottardi@arm.com> | 2021-10-04 16:50:34 +0000 |
| commit | f4962c8d00f00f989b0ecfa0211dc6ec44ec2878 (patch) | |
| tree | 0b5753ec4bdce676f2ad01bef73ced1924ebad7b /scripts/cmake/subsystem-profiles/corstone-sse-300.cmake | |
| parent | 105ed71f09d7959cc28e30a56593f78231b709ee (diff) | |
| download | ml-embedded-evaluation-kit-f4962c8d00f00f989b0ecfa0211dc6ec44ec2878.tar.gz | |
MLECO-2344: Documentation improvement
Documenting how the target platform's SRAM size impacts configuration files,
sources and linker scripts.
Change-Id: I8647ab67b73bafd0c44e6c586a1b5f2602bf03f5
Diffstat (limited to 'scripts/cmake/subsystem-profiles/corstone-sse-300.cmake')
| -rw-r--r-- | scripts/cmake/subsystem-profiles/corstone-sse-300.cmake | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake index 38930af..7e27f3c 100644 --- a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake +++ b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake @@ -17,15 +17,6 @@ # CMake configuration file for peripheral memory map for MPS3 as per SSE-300 design ################################################################################################### -# Application specific config # -################################################################################################### - -# This parameter is based on the linker/scatter script for SSE-300. Do not change this parameter -# in isolation. -set(ACTIVATION_BUF_SRAM_SZ "0x00400000" CACHE STRING "Maximum SRAM size for activation buffers") -set(DESIGN_NAME "Arm Corstone-300 (SSE-300)" CACHE STRING "Design name") - -################################################################################################### # Mem sizes # ################################################################################################### set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB") @@ -67,6 +58,17 @@ set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base ad set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address") ################################################################################################### +# Application specific config # +################################################################################################### + +# This parameter is based on the linker/scatter script for SSE-300. Do not change this parameter +# in isolation. +set(DESIGN_NAME "Arm Corstone-300 (SSE-300)" CACHE STRING "Design name") + +# SRAM size reserved for activation buffers +math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL) + +################################################################################################### # Base addresses for dynamic loads (to be used for FVP form only) # ################################################################################################### # This parameter is also mentioned in the linker/scatter script for SSE-300. Do not change these |