diff options
| author | Cisco Cervellera <cisco.cervellera@arm.com> | 2021-08-02 09:32:07 +0100 |
|---|---|---|
| committer | Isabella Gottardi <isabella.gottardi@arm.com> | 2021-08-03 16:10:16 +0100 |
| commit | f085fa5a2859178741f39563b4d9d68ca41d916a (patch) | |
| tree | 62fd8411c63a853be4c32683a3ada0b6affb0399 /scripts/cmake/subsystem-profiles/corstone-sse-300.cmake | |
| parent | 81c4c9178598e5c26af7373eca67842a8fe4179f (diff) | |
| download | ml-embedded-evaluation-kit-f085fa5a2859178741f39563b4d9d68ca41d916a.tar.gz | |
MLECO-2051: Work with Corstone-300 + Ethos-U65
Change-Id: I64ab930a1de5210f435f91bed7600a700581946f
Signed-off-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-on: https://eu-gerrit-2.euhpc.arm.com/c/ml/ecosystem/ml-embedded-evaluation-kit/+/459126
Tested-by: mlecosys <mlecosys@arm.com>
Tested-by: George Gekov <george.gekov@arm.com>
Reviewed-by: George Gekov <george.gekov@arm.com>
Reviewed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Diffstat (limited to 'scripts/cmake/subsystem-profiles/corstone-sse-300.cmake')
| -rw-r--r-- | scripts/cmake/subsystem-profiles/corstone-sse-300.cmake | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake index 8b565fe..c87dd6a 100644 --- a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake +++ b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake @@ -96,11 +96,11 @@ set(USER_APB3_BASE "0x41703000" CACHE STRING "User APB3") set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ") set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ") -if (ETHOS_U55_ENABLED) - set(ETHOS_U55_BASE "0x48102000" CACHE STRING "Ethos-U55 base address") - set(ETHOS_U55_TA0_BASE "0x48103000" CACHE STRING "Ethos-U55's timing adapter 0 base address") - set(ETHOS_U55_TA1_BASE "0x48103200" CACHE STRING "Ethos-U55's timing adapter 1 base address") -endif (ETHOS_U55_ENABLED) +if (ETHOS_U_NPU_ENABLED) + set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address") + set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") +endif (ETHOS_U_NPU_ENABLED) set(MPS3_I2C0_BASE "0x49200000" CACHE STRING "Touch Screen I2C Base Address ") set(MPS3_I2C1_BASE "0x49201000" CACHE STRING "Audio Interface I2C Base Address ") @@ -156,11 +156,11 @@ set(SEC_USER_APB3_BASE "0x51703000" CACHE STRING "User APB3 Base Address") set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ") set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ") -if (ETHOS_U55_ENABLED) - set(SEC_ETHOS_U55_BASE "0x58102000" CACHE STRING "Ethos-U55 base address") - set(SEC_ETHOS_U55_TA0_BASE "0x58103000" CACHE STRING "Ethos-U55's timing adapter 0 base address") - set(SEC_ETHOS_U55_TA1_BASE "0x58103200" CACHE STRING "Ethos-U55's timing adapter 1 base address") -endif (ETHOS_U55_ENABLED) +if (ETHOS_U_NPU_ENABLED) + set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address") + set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") +endif (ETHOS_U_NPU_ENABLED) set(SEC_MPS3_I2C0_BASE "0x58200000" CACHE STRING "Touch Screen I2C Base Address ") set(SEC_MPS3_I2C1_BASE "0x58201000" CACHE STRING "Audio Interface I2C Base Address ") @@ -243,7 +243,7 @@ set(SPI2_IRQn "53" CACHE STRING " ADC (SPI) Interrupt set(SPI3_IRQn "54" CACHE STRING " SPI 3 Interrupt (Shield 0) ") set(SPI4_IRQn "55" CACHE STRING " SPI 4 Interrupt (Sheild 1) ") -if (ETHOS_U55_ENABLED) +if (ETHOS_U_NPU_ENABLED) set(EthosU_IRQn "56" CACHE STRING " Ethos-U55 Interrupt ") endif () |