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author | Nina Drozd <nina.drozd@arm.com> | 2022-09-05 15:07:56 +0100 |
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committer | Nina Drozd <nina.drozd@arm.com> | 2022-09-05 16:13:32 +0100 |
commit | 72eec15eddf0822a138df029b4afaf2b137dd356 (patch) | |
tree | 33ce32f296d4848b6197ff67f7b13b4378b63275 /docs/sections/timing_adapters.md | |
parent | 6d1e521014fc1db6f587083a2d9b47a03d88af0d (diff) | |
download | ml-embedded-evaluation-kit-72eec15eddf0822a138df029b4afaf2b137dd356.tar.gz |
MLECO-3538: Minor documentation updates
* updated table of contents for building page
* point to timing adapter page
* updates to timing adapter page links and tables
Change-Id: I54bde77db1a082afddae0abe109fa1369506057c
Diffstat (limited to 'docs/sections/timing_adapters.md')
-rw-r--r-- | docs/sections/timing_adapters.md | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/docs/sections/timing_adapters.md b/docs/sections/timing_adapters.md index 5db38c6..c1a9cc0 100644 --- a/docs/sections/timing_adapters.md +++ b/docs/sections/timing_adapters.md @@ -9,7 +9,7 @@ The SRAM is where intermediate buffers are expected to be allocated and therefor and write traffic generated by computation operations while executing a neural network inference. The flash or DDR is where we expect to store the model weights and therefore, this bus would only usually be used for RO traffic. -It is used for MPS3 FPGA and for Fast Model environment (or [AVH](./arm_virtual_hardware.md)). +It is used for MPS3 FPGA and for Fast Model environment (or [AVH](./arm_virtual_hardware.md#overview)). > **NOTE**: All Arm® Corstone™-300 based platform implementations fully support the use of `timing adapter` to perform > bandwidth/latency sweeps for performance estimation of the Arm® Ethos™-U NPUs. However, Arm® Corstone™-310's @@ -146,19 +146,19 @@ not support the feature. Additionally - base addresses of timer adapters blocks ### Timer Adapters for Corstone-300 FVP and FPGA: -| TA# | Interface TA is placed on | Base address (non-secure/secure) | Size | -|-----|---------------------------|----------------------------------|-------| -| 0 | M0/AXI0 for Ethos-U NPU | 0x4810_3000/0x5810_3000 | 0.5KB | -| 1 | M1/AXI1 for Ethos-U NPU | 0x4810_3200/0x5810_3200 | 0.5KB | +| TA Number | Interface TA is placed on | Base address (non-secure/secure) | Size | +|-----------|---------------------------|----------------------------------|-------| +| 0 | M0/AXI0 for Ethos-U NPU | 0x4810_3000/0x5810_3000 | 0.5KB | +| 1 | M1/AXI1 for Ethos-U NPU | 0x4810_3200/0x5810_3200 | 0.5KB | ### Timer Adapter for Corstone-310 FPGA: -| TA# | Interface TA is placed on | Base address (non-secure/secure) | Size | -|-----|---------------------------|----------------------------------|------| -| 0 | FPGA SRAM | 0x4170_0000/0x5170_0000 | 4KB | -| 1 | QSPI flash device | 0x4170_1000/0x5170_1000 | 4KB | -| 2 | DDR | 0x4170_1000/0x5170_2000 | 4KB | -| 3 | User memory | 0x4170_3000/0x5170_3000 | 4KB | +| TA Number | Interface TA is placed on | Base address (non-secure/secure) | Size | +|-----------|---------------------------|----------------------------------|------| +| 0 | FPGA SRAM | 0x4170_0000/0x5170_0000 | 4KB | +| 1 | QSPI flash device | 0x4170_1000/0x5170_1000 | 4KB | +| 2 | DDR | 0x4170_1000/0x5170_2000 | 4KB | +| 3 | User memory | 0x4170_3000/0x5170_3000 | 4KB | This is why the evaluation kit is configured with timing adapters disabled altogether (parameter `ETHOS_U_NPU_TIMING_ADAPTER_ENABLED` set to `OFF`) for Corstone-310 target platform. |