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authorIsabella Gottardi <isabella.gottardi@arm.com>2021-04-07 17:15:31 +0100
committerAlexander Efremov <alexander.efremov@arm.com>2021-04-12 14:00:49 +0000
commit8df12f37531d57a10cba2f8b2e8b6a9065202dd5 (patch)
treeba833d15649c3b0f885d57b40d3916970b3fd2c8 /docs/sections/deployment.md
parent37ce22ebc9cf3e8529d9914c0eed0f718243d961 (diff)
downloadml-embedded-evaluation-kit-8df12f37531d57a10cba2f8b2e8b6a9065202dd5.tar.gz
MLECO-1870: Cherry pick profiling changes from dev to open source repo
* Documentation update Change-Id: If85e7ebc44498840b291c408f14e66a5a5faa424 Signed-off-by: Isabella Gottardi <isabella.gottardi@arm.com>
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1 files changed, 7 insertions, 7 deletions
diff --git a/docs/sections/deployment.md b/docs/sections/deployment.md
index 354d30b..3d5796f 100644
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@@ -267,13 +267,13 @@ off.
7. On the second serial port, output similar to section 2.2 should be visible:
```log
- [INFO] Setting up system tick IRQ (for NPU)
- [INFO] V2M-MPS3 revision C
- [INFO] Application Note AN540, Revision B
- [INFO] FPGA build 1
- [INFO] Core clock has been set to: 32000000 Hz
- [INFO] CPU ID: 0x410fd220
- [INFO] CPU: Cortex-M55 r0p0
+ INFO - Setting up system tick IRQ (for NPU)
+ INFO - V2M-MPS3 revision C
+ INFO - Application Note AN540, Revision B
+ INFO - FPGA build 1
+ INFO - Core clock has been set to: 32000000 Hz
+ INFO - CPU ID: 0x410fd220
+ INFO - CPU: Cortex-M55 r0p0
...
```