diff options
| author | Alex Tawse <alex.tawse@arm.com> | 2024-04-05 11:45:51 +0100 |
|---|---|---|
| committer | Alex Tawse <alex.tawse@arm.com> | 2024-05-20 09:27:19 +0100 |
| commit | 51928a3fd979a36e6c7a9f73bf0ed3bc8a8b7dfd (patch) | |
| tree | 266b4498781c93feebf44808a847f5f6c0c9941b | |
| parent | e0829d313211e5bd0176a6bfef9e07056eb1bbbf (diff) | |
| download | ml-embedded-evaluation-kit-feature/ethos-u85.tar.gz | |
MLECO-4980: Adding Arm Ethos-U85 beta supportfeature/ethos-u85
* Adds beta support for Ethos-U85.
* By default, models will be compiled for
U85-512 as well as the existing U55-128
and U65-256 MAC configurations.
* All U85 MAC configurations are supported.
Change-Id: If11f09c581084b27cf02a91eb74b2b094fe70c3e
Signed-off-by: Alex Tawse <alex.tawse@arm.com>
22 files changed, 820 insertions, 320 deletions
@@ -107,10 +107,11 @@ python3.9 ./build_default.py > > Ml embedded evaluation kit supports: > -> | *Ethos™-U* NPU | Default MACs/cc | Other MACs/cc supported | Default Memory Mode | Other Memory Modes supported | -> |------------------|-----------------|-------------------------|---------------------|------------------------------| -> | *Ethos™-U55* | 128 | 32, 64, 256 | Shared_Sram | Sram_Only | -> | *Ethos™-U65* | 256 | 512 | Dedicated_Sram | Shared_Sram | +> | *Ethos™-U* NPU | Default MACs/cc | Other MACs/cc supported | Default Memory Mode | Other Memory Modes supported | +> |----------------|-----------------|-------------------------|---------------------|------------------------------| +> | *Ethos™-U55* | 128 | 32, 64, 256 | Shared_Sram | Sram_Only | +> | *Ethos™-U65* | 256 | 512 | Dedicated_Sram | Shared_Sram | +> | *Ethos™-U85* | 512 | 128, 256, 1024, 2048 | Dedicated_Sram | Shared_Sram | > > For more information see [Building](./docs/documentation.md#building). diff --git a/build_default.py b/build_default.py index 5adff22..c1af922 100755 --- a/build_default.py +++ b/build_default.py @@ -29,10 +29,10 @@ from dataclasses import dataclass from pathlib import Path from set_up_default_resources import SetupArgs -from set_up_default_resources import default_npu_config_names +from set_up_default_resources import default_npu_configs from set_up_default_resources import get_default_npu_config_from_name from set_up_default_resources import set_up_resources -from set_up_default_resources import valid_npu_config_names +from set_up_default_resources import valid_npu_configs @dataclass(frozen=True) @@ -240,8 +240,8 @@ def run(args: BuildArgs): f"{cmake_path} -B {build_dir} -DTARGET_PLATFORM={target_platform}" f" -DTARGET_SUBSYSTEM={target_subsystem}" f" -DCMAKE_TOOLCHAIN_FILE={cmake_toolchain_file}" - f" -DETHOS_U_NPU_ID={ethos_u_cfg.ethos_u_npu_id}" - f" -DETHOS_U_NPU_CONFIG_ID={ethos_u_cfg.ethos_u_config_id}" + f" -DETHOS_U_NPU_ID={ethos_u_cfg.processor_id}" + f" -DETHOS_U_NPU_CONFIG_ID={ethos_u_cfg.config_id}" " -DTENSORFLOW_LITE_MICRO_CLEAN_DOWNLOADS=ON" ) @@ -279,8 +279,8 @@ if __name__ == "__main__": parser.add_argument( "--npu-config-name", help=f"""Arm Ethos-U configuration to build for. Choose from: - {valid_npu_config_names}""", - default=default_npu_config_names[0], + {valid_npu_configs.names}""", + default=default_npu_configs.names[0], ) parser.add_argument( "--make-jobs", diff --git a/dependencies/core-driver b/dependencies/core-driver -Subproject 0189cd2b334b2d88302d13d6003c50a642db0bb +Subproject 9622608a5cc318c0933bcce720b59737d03bfb6 diff --git a/docs/quick_start.md b/docs/quick_start.md index daef495..783a0eb 100644 --- a/docs/quick_start.md +++ b/docs/quick_start.md @@ -156,6 +156,14 @@ mv resources_downloaded/kws/kws_micronet_m.tflite resources_downloaded/kws/kws_m --output-dir=resources_downloaded/kws mv resources_downloaded/kws/kws_micronet_vela.tflite resources_downloaded/kws/kws_micronet_m_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/kws/kws_micronet_m.tflite \ + --accelerator-config=ethos-u85-512 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_SYS_DRAM_Mid_512 \ + --output-dir=resources_downloaded/kws +mv resources_downloaded/kws/kws_micronet_vela.tflite resources_downloaded/kws/kws_micronet_m_vela_Z512.tflite + . resources_downloaded/env/bin/activate && vela resources_downloaded/kws_asr/wav2letter_int8.tflite \ --accelerator-config=ethos-u55-128 \ --optimise Performance --config scripts/vela/default_vela.ini \ @@ -173,6 +181,14 @@ mv resources_downloaded/kws_asr/wav2letter_int8_vela.tflite resources_downloaded --output-dir=resources_downloaded/kws_asr mv resources_downloaded/kws_asr/wav2letter_int8_vela.tflite resources_downloaded/kws_asr/wav2letter_int8_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/kws_asr/wav2letter_int8.tflite \ + --accelerator-config=ethos-u85-512 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_SYS_DRAM_Mid_512 \ + --output-dir=resources_downloaded/kws_asr +mv resources_downloaded/kws_asr/wav2letter_int8_vela.tflite resources_downloaded/kws_asr/wav2letter_int8_vela_Z512.tflite + . resources_downloaded/env/bin/activate && vela resources_downloaded/kws_asr/kws_micronet_m.tflite \ --accelerator-config=ethos-u55-128 \ --optimise Performance --config scripts/vela/default_vela.ini \ @@ -190,6 +206,14 @@ mv resources_downloaded/kws_asr/kws_micronet_m.tflite_vela.tflite resources_down --output-dir=resources_downloaded/kws_asr mv resources_downloaded/kws_asr/kws_micronet_m.tflite_vela.tflite resources_downloaded/kws_asr/kws_micronet_m.tflite_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/kws_asr/kws_micronet_m.tflite \ + --accelerator-config=ethos-u85-512 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_SYS_DRAM_Mid_512 \ + --output-dir=resources_downloaded/kws_asr +mv resources_downloaded/kws_asr/kws_micronet_m.tflite_vela.tflite resources_downloaded/kws_asr/kws_micronet_m.tflite_vela_Y256.tflite + . resources_downloaded/env/bin/activate && vela resources_downloaded/inference_runner/dnn_s_quantized.tflite \ --accelerator-config=ethos-u55-128 \ --optimise Performance --config scripts/vela/default_vela.ini \ @@ -207,6 +231,14 @@ mv resources_downloaded/inference_runner/dnn_s_quantized_vela.tflite resources_d --output-dir=resources_downloaded/inference_runner mv resources_downloaded/inference_runner/dnn_s_quantized_vela.tflite resources_downloaded/inference_runner/dnn_s_quantized_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/inference_runner/dnn_s_quantized.tflite \ + --accelerator-config=ethos-u85-512 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_SYS_DRAM_Mid_512 \ + --output-dir=resources_downloaded/inference_runner +mv resources_downloaded/inference_runner/dnn_s_quantized_vela.tflite resources_downloaded/inference_runner/dnn_s_quantized_vela_Z512.tflite + . resources_downloaded/env/bin/activate && vela resources_downloaded/img_class/mobilenet_v2_1.0_224_INT8.tflite \ --accelerator-config=ethos-u55-128 \ --optimise Performance --config scripts/vela/default_vela.ini \ @@ -224,6 +256,14 @@ mv resources_downloaded/img_class/mobilenet_v2_1.0_224_INT8_vela.tflite resource --output-dir=resources_downloaded/img_class mv resources_downloaded/img_class/mobilenet_v2_1.0_224_INT8_vela.tflite resources_downloaded/img_class/mobilenet_v2_1.0_224_INT8_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/img_class/mobilenet_v2_1.0_224_INT8.tflite \ + --accelerator-config=ethos-u65-512 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_High_End \ + --output-dir=resources_downloaded/img_class +mv resources_downloaded/img_class/mobilenet_v2_1.0_224_INT8_vela.tflite resources_downloaded/img_class/mobilenet_v2_1.0_224_INT8_vela_Z512.tflite + . resources_downloaded/env/bin/activate && vela resources_downloaded/asr/wav2letter_int8.tflite \ --accelerator-config=ethos-u55-128 \ --optimise Performance --config scripts/vela/default_vela.ini \ @@ -241,6 +281,14 @@ mv resources_downloaded/asr/wav2letter_int8_vela.tflite resources_downloaded/asr --output-dir=resources_downloaded/asr mv resources_downloaded/asr/wav2letter_int8_vela.tflite resources_downloaded/asr/wav2letter_int8_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/asr/wav2letter_int8.tflite \ + --accelerator-config=ethos-u85-256 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_SYS_DRAM_Mid_512 \ + --output-dir=resources_downloaded/asr +mv resources_downloaded/asr/wav2letter_int8_vela.tflite resources_downloaded/asr/wav2letter_int8_vela_Z512.tflite + . resources_downloaded/env/bin/activate && vela resources_downloaded/ad/ad_medium_int8.tflite \ --accelerator-config=ethos-u55-128 \ --optimise Performance --config scripts/vela/default_vela.ini \ @@ -258,6 +306,14 @@ mv resources_downloaded/ad/ad_medium_int8_vela.tflite resources_downloaded/ad/ad --output-dir=resources_downloaded/ad mv resources_downloaded/ad/ad_medium_int8_vela.tflite resources_downloaded/ad/ad_medium_int8_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/ad/ad_medium_int8.tflite \ + --accelerator-config=ethos-u85-512 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_SYS_DRAM_Mid_512 \ + --output-dir=resources_downloaded/ad +mv resources_downloaded/ad/ad_medium_int8_vela.tflite resources_downloaded/ad/ad_medium_int8_vela_Z512.tflite + . resources_downloaded/env/bin/activate && vela resources_downloaded/vww/vww4_128_128_INT8.tflite \ --accelerator-config=ethos-u55-128 \ --optimise Performance --config scripts/vela/default_vela.ini \ @@ -275,6 +331,14 @@ mv resources_downloaded/vww/vww4_128_128_INT8_vela.tflite resources_downloaded/v --output-dir=resources_downloaded/ad mv resources_downloaded/vww/vww4_128_128_INT8_vela.tflite resources_downloaded/vww/vww4_128_128_INT8_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/vww/vww4_128_128_INT8.tflite \ + --accelerator-config=ethos-u85-512 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_SYS_DRAM_Mid_512 \ + --output-dir=resources_downloaded/ad +mv resources_downloaded/vww/vww4_128_128_INT8_vela.tflite resources_downloaded/vww/vww4_128_128_INT8_vela_Z512.tflite + . resources_downloaded/env/bin/activate && vela resources_downloaded/noise_reduction/rnnoise_INT8.tflite \ --accelerator-config=ethos-u55-128 \ --optimise Performance --config scripts/vela/default_vela.ini \ @@ -292,6 +356,14 @@ mv resources_downloaded/noise_reduction/rnnoise_INT8_vela.tflite resources_downl --output-dir=resources_downloaded/ad mv resources_downloaded/noise_reduction/rnnoise_INT8_vela.tflite resources_downloaded/noise_reduction/rnnoise_INT8_vela_Y256.tflite +. resources_downloaded/env/bin/activate && vela resources_downloaded/noise_reduction/rnnoise_INT8.tflite \ + --accelerator-config=ethos-u85-512 \ + --optimise Performance --config scripts/vela/default_vela.ini \ + --memory-mode=Dedicated_Sram \ + --system-config=Ethos_U85_SYS_DRAM_Mid_512 \ + --output-dir=resources_downloaded/ad +mv resources_downloaded/noise_reduction/rnnoise_INT8_vela.tflite resources_downloaded/noise_reduction/rnnoise_INT8_vela_Z512.tflite + mkdir cmake-build-mps3-sse-300-gnu-release and cd cmake-build-mps3-sse-300-gnu-release cmake .. \ diff --git a/docs/sections/building.md b/docs/sections/building.md index 775f71a..e5449b2 100644 --- a/docs/sections/building.md +++ b/docs/sections/building.md @@ -167,7 +167,7 @@ along with the network inputs. It also builds TensorFlow Lite for Microcontrollers library, Arm® *Ethos™-U* NPU driver library, and the CMSIS-DSP library from sources. -The build script is parameterized to support different options (see [common_user_options.cmake](../../scripts/cmake/common_user_options.cmake)). +The build script is parameterized to support different options (see [common_opts.cmake](../../scripts/configuration_options/common_opts.cmake)). Default values for these parameters configure the build for all use-cases to be executed on an MPS3 FPGA or the Fixed Virtual Platform (FVP) implementation of the Arm® *Corstone™-300* design. @@ -209,19 +209,21 @@ The build parameters are: - `ETHOS_U_NPU_ID`: The *Ethos-U* NPU processor: - `U55` (default) - `U65` + - `U85` - `ETHOS_U_NPU_MEMORY_MODE`: The *Ethos-U* NPU memory mode: - `Shared_Sram` (default for *Ethos-U55* NPU) - - `Dedicated_Sram` (default for *Ethos-U65* NPU) + - `Dedicated_Sram` (default for *Ethos-U65* and *Ethos-U85* NPU) - `Sram_Only` - > **Note:** The `Shared_Sram` memory mode is available on both *Ethos-U55* and *Ethos-U65* NPU, `Dedicated_Sram` only - > for *Ethos-U65* NPU and `Sram_Only` only for *Ethos-U55* NPU. + > **Note:** The `Shared_Sram` memory mode is available on *Ethos-U55*, *Ethos-U65* and *Ethos-U85* NPU, + > `Dedicated_Sram` only for *Ethos-U65* and *Ethos-U85* NPU and `Sram_Only` only for *Ethos-U55* NPU. - `ETHOS_U_NPU_CONFIG_ID`: This parameter is set by default based on the value of `ETHOS_U_NPU_ID`. For Ethos-U55, it defaults to the `H128` indicating that the Ethos-U55 128 MAC optimised model - should be used. For Ethos-U65, it defaults to `Y256` instead. However, the user can override these - defaults to a configuration ID from `H32`, `H64`, `H256` and `Y512`. + should be used. For Ethos-U65, it defaults to `Y256` and for Ethos-U85 it defaults to `Z512`. + However, the user can override these defaults to a configuration ID from `H32`, `H64`, `H256`, `Y512`, + `Z128`, `Z256`, `Z1024` and `Z2048`. > **Note:** This ID is only used to choose which tflite file path is to be used by the CMake > configuration for all the use cases. If the user has overridden use-case specific model path @@ -231,7 +233,8 @@ The build parameters are: > chosen configuration. - `ETHOS_U_NPU_CACHE_SIZE`: The *Ethos-U* NPU cache size used if the *Ethos-U* NPU processor selected with the option - `ETHOS_U_NPU_ID` is `U65`. Default value is 393216 (see [default_vela.ini](../../scripts/vela/default_vela.ini) ). + `ETHOS_U_NPU_ID` is `U65` or `U85`. + Default value is 393216 (see [default_vela.ini](../../scripts/vela/default_vela.ini) ). - `CPU_PROFILE_ENABLED`: Sets whether profiling information for the CPU core should be displayed. By default, this is set to false, but can be turned on for FPGA targets. The FVP and the CPU core cycle counts are **not** meaningful and @@ -266,7 +269,8 @@ The build parameters are: - `TA_CONFIG_FILE`: The path to the CMake configuration file that contains the timing adapter parameters. Used only if the timing adapter build is enabled. Default for Ethos-U55 NPU is [ta_config_u55_high_end.cmake](../../scripts/timing_adapter/ta_config_u55_high_end.cmake), - for Ethos-U65 NPU is [ta_config_u55_high_end.cmake](../../scripts/timing_adapter/ta_config_u55_high_end.cmake). + for Ethos-U65 NPU is [ta_config_u55_high_end.cmake](../../scripts/timing_adapter/ta_config_u55_high_end.cmake) and + for Ethos-U85 NPU is [ta_config_u85_high_end.cmake](../../scripts/timing_adapter/ta_config_u85_high_end.cmake). - `TENSORFLOW_LITE_MICRO_CLEAN_BUILD`: Optional parameter to enable, or disable, "cleaning" prior to building for the TensorFlow Lite Micro library. Enabled by default. @@ -357,8 +361,8 @@ python3 ./set_up_default_resources.py ``` This fetches every model into the `resources_downloaded` directory. It also optimizes the models using the Vela compiler -for the default 128 MACs configuration of the Arm® *Ethos™-U55* NPU and for the default 256 MACs configuration of the -Arm® *Ethos™-U65* NPU. +for the default 128 MACs configuration of the Arm® *Ethos™-U55* NPU, the default 256 MACs configuration of the +Arm® *Ethos™-U65* NPU and the 512 MACs configuration of the Arm® *Ethos™-U85* NPU. > **Note:** This script requires Python version 3.10 or higher. Please make sure all [build prerequisites](./building.md#build-prerequisites) > are satisfied. If your environment points to system installed Python3 that is an older version than 3.10, choose the @@ -381,15 +385,16 @@ Additional command line arguments supported by this script are: --additional-ethos-u-config-name ethos-u65-512 ``` - > **Note:** As the argument name suggests, the configuration names are **in addition to** the default ones: `ethos-u55-128` - > and `ethosu-u65-256`. + > **Note:** As the argument name suggests, the configuration names are **in addition to** the default ones: + > `ethos-u55-128`, `ethosu-u65-256` and `ethosu-u85-512`. - `--arena-cache-size`: the size of the arena cache memory area, in bytes. The default value is: - the internal SRAM size for Corstone-300 implementation on MPS3 specified by AN552, when optimizing for the default 128 MACs configuration of the Arm® *Ethos™-U55* NPU. - the default value specified in the Vela configuration file [default_vela.ini](../../scripts/vela/default_vela.ini), - when optimizing for the default 256 MACs configuration of the Arm® *Ethos™-U65* NPU. + when optimizing for the default 256 MACs configuration of the Arm® *Ethos™-U65* NPU + or the default 512 MACs configuration of the Arm® *Ethos™-U85* NPU. ### Building for default configuration @@ -421,7 +426,11 @@ Additional command line arguments supported by this script are: - `ethos-u55-128` - `ethos-u55-256` - `ethos-u65-256` - - `ethos-u65-512` + - `ethos-u65-128` + - `ethos-u85-256` + - `ethos-u85-512` + - `ethos-u85-1024` + - `ethos-u85-2048` - `--make-jobs`: Specifies the number of concurrent jobs to use for compilation. The default value is equal to the number of cores in the system. Lowering this value can be useful in case of limited resources. @@ -744,7 +753,8 @@ vela \ The Vela command contains the following: - `--accelerator-config`: Specifies the accelerator configuration to use between `ethos-u55-256`, `ethos-u55-128`, - `ethos-u55-64`, `ethos-u55-32`, `ethos-u65-256`, and `ethos-u65-512`. + `ethos-u55-64`, `ethos-u55-32`, `ethos-u65-256`, `ethos-u65-512`, `ethos-u85-128`, `ethos-u85-256`, `ethos-u85-512`, + `ethos-u85-1024` and `ethos-u85-2048`. - `--optimise`: Sets the optimisation strategy to Performance or Size. The Size strategy results in a model minimising the SRAM usage whereas the Performance strategy optimises the neural network for maximal performance. Note that if using the Performance strategy, you can also pass the `--arena-cache-size` option to Vela. @@ -752,7 +762,11 @@ The Vela command contains the following: file. An example can be found in the `dependencies` folder [default_vela.ini](../../scripts/vela/default_vela.ini). - `--memory-mode`: Selects the memory mode to use as specified in the Vela configuration file. - `--system-config`: Selects the system configuration to use as specified in the Vela configuration file: - `Ethos_U55_High_End_Embedded`for *Ethos-U55* and `Ethos_U65_High_End` for *Ethos-U65*. + `Ethos_U55_High_End_Embedded`for *Ethos-U55*, `Ethos_U65_High_End` for *Ethos-U65*, + `Ethos_U85_SYS_DRAM_Low` for *Ethos-U85* with 128 or 256 MACs configurations, + `Ethos_U85_SYS_DRAM_Mid_512` for *Ethos-U85* with 512 MACs configuration, + `Ethos_U85_SYS_DRAM_Mid_1024` for *Ethos-U85* with 1024 MACs configuration and + `Ethos_U85_SYS_DRAM_Mid_2048` for *Ethos-U85* with 2048 MACs configuration. Vela compiler accepts `.tflite` file as input and saves optimized network model as a `.tflite` file. @@ -776,7 +790,7 @@ using the *Ethos-U55* High End timing adapter system configuration. To build for a different *Ethos-U* NPU variant: - Optimize the model with Vela compiler with the correct parameters. See [Optimize custom model with Vela compiler](./building.md#optimize-custom-model-with-vela-compiler). -- Use the correct `ETHOS_U_NPU_ID`: `U55` for *Ethos-U55* NPU, `U65` for *Ethos-U65* NPU. +- Use the correct `ETHOS_U_NPU_ID`: `U55` for *Ethos-U55* NPU, `U65` for *Ethos-U65* NPU or `U85` for *Ethos-U85*. - Use the Vela model as custom model in the building command. See [Add custom model](./building.md#add-custom-model) - Use the correct timing adapter settings configuration. See [Building timing adapter with custom options](./building.md#building-timing-adapter-with-custom-options) diff --git a/docs/sections/memory_considerations.md b/docs/sections/memory_considerations.md index 30b36ac..20c6007 100644 --- a/docs/sections/memory_considerations.md +++ b/docs/sections/memory_considerations.md @@ -77,7 +77,7 @@ Other than the obvious link between the linker script and the target profile des CMake files, there are other parameters linked to what the reserved space for activation buffers is. These are: -- The file [set_up_default_resources.py](../../set_up_default_resources.py) contains a +- The file [vela_configs.py](../../scripts/py/vela_configs.py) contains a parameter called `mps3_max_sram_sz`: ```python diff --git a/docs/sections/timing_adapters.md b/docs/sections/timing_adapters.md index 24f2fc9..f232450 100644 --- a/docs/sections/timing_adapters.md +++ b/docs/sections/timing_adapters.md @@ -66,26 +66,26 @@ The CMake build framework allows the parameters to control the behavior of each For the CMake build configuration of the timing adapter, the SRAM AXI is assigned `index 0` and the flash, or DRAM, AXI bus has `index 1`. -To change the bus parameter for the build a "***TA_\<index>_*"** prefix should be added to the above. For example, -**TA0_MAXR=10** sets the maximum pending reads to 10 on the SRAM AXI bus. +To change the bus parameter for the build an "***SRAM***" or "***EXT***" prefix should be added to the above. For example, +**SRAM_MAXR=10** sets the maximum pending reads to 10 on the SRAM AXI bus. As an example, if we have the following parameters for the flash, or DRAM, region: -- `TA1_MAXR` = "2" +- `EXT_MAXR` = "2" -- `TA1_MAXW` = "0" +- `EXT_MAXW` = "0" -- `TA1_MAXRW` = "0" +- `EXT_MAXRW` = "0" -- `TA1_RLATENCY` = "64" +- `EXT_RLATENCY` = "64" -- `TA1_WLATENCY` = "32" +- `EXT_WLATENCY` = "32" -- `TA1_PULSE_ON` = "320" +- `EXT_PULSE_ON` = "320" -- `TA1_PULSE_OFF` = "80" +- `EXT_PULSE_OFF` = "80" -- `TA1_BWCAP` = "50" +- `EXT_BWCAP` = "50" For a clock rate of 500MHz, this would translate to: @@ -109,24 +109,21 @@ For a clock rate of 500MHz, this would translate to: This suggests that the read operation is only limited by the overall bus bandwidth. Timing adapter requires recompilation to change parameters. Default timing adapter configuration file pointed to by -`TA_CONFIG_FILE` build parameter is located in the `scripts/cmake folder` and contains all options for `AXI0` and `AXI1` +`TA_CONFIG_FILE` build parameter is located in the `scripts/cmake folder` and contains all options for `SRAM` and `EXT` as previously described. here is an example of `scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake`: ```cmake -# Timing adapter options -set(TA_INTERACTIVE OFF) - -# Timing adapter settings for AXI0 -set(TA0_MAXR "8") -set(TA0_MAXW "8") -set(TA0_MAXRW "0") -set(TA0_RLATENCY "32") -set(TA0_WLATENCY "32") -set(TA0_PULSE_ON "3999") -set(TA0_PULSE_OFF "1") -set(TA0_BWCAP "4000") +# Timing adapter settings for SRAM +set(SRAM_MAXR "8") +set(SRAM_MAXW "8") +set(SRAM_MAXRW "0") +set(SRAM_RLATENCY "32") +set(SRAM_WLATENCY "32") +set(SRAM_PULSE_ON "3999") +set(SRAM_PULSE_OFF "1") +set(SRAM_BWCAP "4000") ... ``` @@ -148,8 +145,8 @@ not support the feature. Additionally - base addresses of timer adapters blocks | TA Number | Interface TA is placed on | Base address (non-secure/secure) | Size | |-----------|---------------------------|----------------------------------|-------| -| 0 | M0/AXI0 for Ethos-U NPU | 0x4810_3000/0x5810_3000 | 0.5KB | -| 1 | M1/AXI1 for Ethos-U NPU | 0x4810_3200/0x5810_3200 | 0.5KB | +| 0 | M0/SRAM0 for Ethos-U NPU | 0x4810_3000/0x5810_3000 | 0.5KB | +| 1 | M1/EXT0 for Ethos-U NPU | 0x4810_3200/0x5810_3200 | 0.5KB | ### Timer Adapter for Corstone-310 FPGA: diff --git a/scripts/cmake/configuration_options/npu_opts.cmake b/scripts/cmake/configuration_options/npu_opts.cmake index c947ac9..867fdf0 100644 --- a/scripts/cmake/configuration_options/npu_opts.cmake +++ b/scripts/cmake/configuration_options/npu_opts.cmake @@ -49,21 +49,27 @@ USER_OPTION(ETHOS_U_NPU_ID "Arm Ethos-U NPU IP (U55 or U65)" "U55" STRING) -if ((ETHOS_U_NPU_ID STREQUAL U55) OR (ETHOS_U_NPU_ID STREQUAL U65)) - if (ETHOS_U_NPU_ID STREQUAL U55) - set(DEFAULT_NPU_MEM_MODE "Shared_Sram") - set(DEFAULT_NPU_CONFIG_ID "H128") - elseif(ETHOS_U_NPU_ID STREQUAL U65) - set(DEFAULT_NPU_MEM_MODE "Dedicated_Sram") - set(DEFAULT_NPU_CONFIG_ID "Y256") - set(DEFAULT_NPU_CACHE_SIZE "393216") +if (ETHOS_U_NPU_ID STREQUAL U55) + set(DEFAULT_NPU_MEM_MODE "Shared_Sram") + set(DEFAULT_NPU_CONFIG_ID "H128") + set(DEFAULT_TA_CONFIG_FILE "ta_config_u55_high_end") +elseif (ETHOS_U_NPU_ID STREQUAL U65) + set(DEFAULT_NPU_MEM_MODE "Dedicated_Sram") + set(DEFAULT_NPU_CONFIG_ID "Y256") + set(DEFAULT_TA_CONFIG_FILE "ta_config_u65_high_end") +elseif (ETHOS_U_NPU_ID STREQUAL U85) + set(DEFAULT_NPU_MEM_MODE "Dedicated_Sram") + set(DEFAULT_NPU_CONFIG_ID "Z512") + set(DEFAULT_TA_CONFIG_FILE "ta_config_u85_high_end") +else() + message(FATAL_ERROR "Non compatible Ethos-U NPU processor ${ETHOS_U_NPU_ID}") +endif() - USER_OPTION(ETHOS_U_NPU_CACHE_SIZE "Arm Ethos-U65 NPU Cache Size" +if(DEFAULT_NPU_MEM_MODE STREQUAL "Dedicated_Sram") + set(DEFAULT_NPU_CACHE_SIZE "393216") + USER_OPTION(ETHOS_U_NPU_CACHE_SIZE "Arm Ethos-U NPU Cache Size" "${DEFAULT_NPU_CACHE_SIZE}" STRING) - endif() -else () - message(FATAL_ERROR "Non compatible Ethos-U NPU processor ${ETHOS_U_NPU_ID}") endif () USER_OPTION(ETHOS_U_NPU_MEMORY_MODE "Specifies the memory mode used in the Vela command." @@ -74,12 +80,6 @@ USER_OPTION(ETHOS_U_NPU_CONFIG_ID "Specifies the configuration ID for the NPU." "${DEFAULT_NPU_CONFIG_ID}" STRING) -if (ETHOS_U_NPU_ID STREQUAL U55) - set(DEFAULT_TA_CONFIG_FILE "ta_config_u55_high_end") -else () - set(DEFAULT_TA_CONFIG_FILE "ta_config_u65_high_end") -endif () - USER_OPTION(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED "Specifies if the Ethos-U timing adapter is enabled" ON BOOL) diff --git a/scripts/cmake/platforms/mps3/build_configuration.cmake b/scripts/cmake/platforms/mps3/build_configuration.cmake index c29531f..aa521bf 100644 --- a/scripts/cmake/platforms/mps3/build_configuration.cmake +++ b/scripts/cmake/platforms/mps3/build_configuration.cmake @@ -121,6 +121,11 @@ function(platform_custom_post_build) set(AXF_PATH "${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.axf") set(TEST_TARGET_NAME "${use_case}_fvp_test") + set(FVP_CONFIG_ARG "") + if (ETHOS_U_NPU_ID STREQUAL "U85") + set(FVP_CONFIG_ARG -C ethosu.config="${ETHOS_U_NPU_CONFIG_ID}") + endif () + message(STATUS "Adding FVP test for ${use_case}") add_test( @@ -130,6 +135,7 @@ function(platform_custom_post_build) -C mps3_board.uart0.out_file='-' -C mps3_board.uart0.shutdown_on_eot=1 -C mps3_board.visualisation.disable-visualisation=1 + ${FVP_CONFIG_ARG} --stat) endif() endif () diff --git a/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake b/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake index 37785e3..8ccf3b6 100644 --- a/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake +++ b/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake @@ -23,67 +23,67 @@ # The platform CMake infra should set the base register values for # TA component to work. For Ethos-U55, we need two base addresses. -if (NOT DEFINED TA0_BASE OR NOT DEFINED TA1_BASE) - message(FATAL_ERROR "TA0_BASE and TA1_BASE need to be defined.") +if (NOT DEFINED TA_SRAM0_BASE OR NOT DEFINED TA_EXT0_BASE) + message(FATAL_ERROR "TA_SRAM0_BASE and TA_EXT0_BASE need to be defined.") endif () -message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.") +message(STATUS "using TA_SRAM0_BASE @ ${TA_SRAM0_BASE}; TA_EXT0_BASE @ ${TA_EXT0_BASE}.") -# Timing adapter settings for AXI0 -set(TA0_MAXR "8" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") -set(TA0_MAXW "8" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") -set(TA0_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") -set(TA0_RLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") -set(TA0_WLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") -set(TA0_PULSE_ON "3999" CACHE STRING "No. of cycles addresses let through (0-65535).") -set(TA0_PULSE_OFF "1" CACHE STRING "No. of cycles addresses blocked (0-65535).") -set(TA0_BWCAP "4000" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") -set(TA0_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") -set(TA0_PERFCNT "0" CACHE STRING "32-bit event counter") -set(TA0_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; +# Timing adapter settings for SRAM +set(SRAM_MAXR "8" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") +set(SRAM_MAXW "8" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") +set(SRAM_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") +set(SRAM_RLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") +set(SRAM_WLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") +set(SRAM_PULSE_ON "3999" CACHE STRING "No. of cycles addresses let through (0-65535).") +set(SRAM_PULSE_OFF "1" CACHE STRING "No. of cycles addresses blocked (0-65535).") +set(SRAM_BWCAP "4000" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") +set(SRAM_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") +set(SRAM_PERFCNT "0" CACHE STRING "32-bit event counter") +set(SRAM_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; Bit 1: 1=enable random AR reordering (0=default); Bit 2: 1=enable random R reordering (0=default); Bit 3: 1=enable random B reordering (0=default); Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") -set(TA0_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") -set(TA0_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") +set(SRAM_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") +set(SRAM_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") -# Timing adapter settings for AXI1 -# If Memory mode is Sram_Only Timing adapter settings for AXI1 need to match the same as AXI0 +# Timing adapter settings for EXT +# If Memory mode is Sram_Only Timing adapter settings for EXT need to match the same as SRAM if (ETHOS_U_NPU_MEMORY_MODE STREQUAL Sram_Only) - set(TA1_MAXR ${TA0_MAXR} CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") - set(TA1_MAXW ${TA0_MAXW} CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") - set(TA1_MAXRW ${TA0_MAXRW} CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") - set(TA1_RLATENCY ${TA0_RLATENCY} CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") - set(TA1_WLATENCY ${TA0_WLATENCY} CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") - set(TA1_PULSE_ON ${TA0_PULSE_ON} CACHE STRING "No. of cycles addresses let through (0-65535).") - set(TA1_PULSE_OFF ${TA0_PULSE_OFF} CACHE STRING "No. of cycles addresses blocked (0-65535).") - set(TA1_BWCAP ${TA0_BWCAP} CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") - set(TA1_PERFCTRL ${TA0_PERFCTRL} CACHE STRING "6-bit field selecting an event for event counter 0=default") - set(TA1_PERFCNT ${TA0_PERFCNT} CACHE STRING "32-bit event counter") - set(TA1_MODE ${TA0_MODE} CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; + set(EXT_MAXR ${SRAM_MAXR} CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") + set(EXT_MAXW ${SRAM_MAXW} CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") + set(EXT_MAXRW ${SRAM_MAXRW} CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") + set(EXT_RLATENCY ${SRAM_RLATENCY} CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") + set(EXT_WLATENCY ${SRAM_WLATENCY} CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") + set(EXT_PULSE_ON ${SRAM_PULSE_ON} CACHE STRING "No. of cycles addresses let through (0-65535).") + set(EXT_PULSE_OFF ${SRAM_PULSE_OFF} CACHE STRING "No. of cycles addresses blocked (0-65535).") + set(EXT_BWCAP ${SRAM_BWCAP} CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") + set(EXT_PERFCTRL ${SRAM_PERFCTRL} CACHE STRING "6-bit field selecting an event for event counter 0=default") + set(EXT_PERFCNT ${SRAM_PERFCNT} CACHE STRING "32-bit event counter") + set(EXT_MODE ${SRAM_MODE} CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; Bit 1: 1=enable random AR reordering (0=default); Bit 2: 1=enable random R reordering (0=default); Bit 3: 1=enable random B reordering (0=default); Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") - set(TA1_HISTBIN ${TA0_HISTBIN} CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") - set(TA1_HISTCNT ${TA0_HISTCNT} CACHE STRING "32-bit field. Read/write the selected histogram bin.") + set(EXT_HISTBIN ${SRAM_HISTBIN} CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") + set(EXT_HISTCNT ${SRAM_HISTCNT} CACHE STRING "32-bit field. Read/write the selected histogram bin.") else () - set(TA1_MAXR "2" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") - set(TA1_MAXW "0" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") - set(TA1_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") - set(TA1_RLATENCY "64" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") - set(TA1_WLATENCY "0" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") - set(TA1_PULSE_ON "320" CACHE STRING "No. of cycles addresses let through (0-65535).") - set(TA1_PULSE_OFF "80" CACHE STRING "No. of cycles addresses blocked (0-65535).") - set(TA1_BWCAP "50" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") - set(TA1_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") - set(TA1_PERFCNT "0" CACHE STRING "32-bit event counter") - set(TA1_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; + set(EXT_MAXR "2" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") + set(EXT_MAXW "0" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") + set(EXT_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") + set(EXT_RLATENCY "64" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") + set(EXT_WLATENCY "0" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") + set(EXT_PULSE_ON "320" CACHE STRING "No. of cycles addresses let through (0-65535).") + set(EXT_PULSE_OFF "80" CACHE STRING "No. of cycles addresses blocked (0-65535).") + set(EXT_BWCAP "50" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") + set(EXT_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") + set(EXT_PERFCNT "0" CACHE STRING "32-bit event counter") + set(EXT_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; Bit 1: 1=enable random AR reordering (0=default); Bit 2: 1=enable random R reordering (0=default); Bit 3: 1=enable random B reordering (0=default); Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") - set(TA1_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") - set(TA1_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") + set(EXT_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") + set(EXT_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") endif ()
\ No newline at end of file diff --git a/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake b/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake index e29d144..ce36be8 100644 --- a/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake +++ b/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake @@ -23,46 +23,46 @@ # The platform CMake infra should set the base register values for # TA component to work. For Ethos-U65, we need two base addresses. -if (NOT DEFINED TA0_BASE OR NOT DEFINED TA1_BASE) - message(FATAL_ERROR "TA0_BASE and TA1_BASE need to be defined.") +if (NOT DEFINED TA_SRAM0_BASE OR NOT DEFINED TA_EXT0_BASE) + message(FATAL_ERROR "TA_SRAM0_BASE and TA_EXT0_BASE need to be defined.") endif () -message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.") +message(STATUS "using TA_SRAM0_BASE @ ${TA_SRAM0_BASE}; TA_EXT0_BASE @ ${TA_EXT0_BASE}.") # Timing adapter settings for AXI0 -set(TA0_MAXR "16" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") -set(TA0_MAXW "16" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") -set(TA0_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") -set(TA0_RLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") -set(TA0_WLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") -set(TA0_PULSE_ON "3999" CACHE STRING "No. of cycles addresses let through (0-65535).") -set(TA0_PULSE_OFF "1" CACHE STRING "No. of cycles addresses blocked (0-65535).") -set(TA0_BWCAP "4000" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") -set(TA0_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") -set(TA0_PERFCNT "0" CACHE STRING "32-bit event counter") -set(TA0_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; +set(SRAM_MAXR "16" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") +set(SRAM_MAXW "16" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") +set(SRAM_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") +set(SRAM_RLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") +set(SRAM_WLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") +set(SRAM_PULSE_ON "3999" CACHE STRING "No. of cycles addresses let through (0-65535).") +set(SRAM_PULSE_OFF "1" CACHE STRING "No. of cycles addresses blocked (0-65535).") +set(SRAM_BWCAP "4000" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") +set(SRAM_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") +set(SRAM_PERFCNT "0" CACHE STRING "32-bit event counter") +set(SRAM_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; Bit 1: 1=enable random AR reordering (0=default); Bit 2: 1=enable random R reordering (0=default); Bit 3: 1=enable random B reordering (0=default); Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") -set(TA0_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") -set(TA0_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") +set(SRAM_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") +set(SRAM_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") # Timing adapter settings for AXI1 -set(TA1_MAXR "24" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") -set(TA1_MAXW "12" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") -set(TA1_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") -set(TA1_RLATENCY "500" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") -set(TA1_WLATENCY "250" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") -set(TA1_PULSE_ON "4000" CACHE STRING "No. of cycles addresses let through (0-65535).") -set(TA1_PULSE_OFF "1000" CACHE STRING "No. of cycles addresses blocked (0-65535).") -set(TA1_BWCAP "1172" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") -set(TA1_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") -set(TA1_PERFCNT "0" CACHE STRING "32-bit event counter") -set(TA1_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; +set(EXT_MAXR "24" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") +set(EXT_MAXW "12" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") +set(EXT_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") +set(EXT_RLATENCY "500" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") +set(EXT_WLATENCY "250" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") +set(EXT_PULSE_ON "4000" CACHE STRING "No. of cycles addresses let through (0-65535).") +set(EXT_PULSE_OFF "1000" CACHE STRING "No. of cycles addresses blocked (0-65535).") +set(EXT_BWCAP "1172" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") +set(EXT_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") +set(EXT_PERFCNT "0" CACHE STRING "32-bit event counter") +set(EXT_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; Bit 1: 1=enable random AR reordering (0=default); Bit 2: 1=enable random R reordering (0=default); Bit 3: 1=enable random B reordering (0=default); Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") -set(TA1_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") -set(TA1_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") +set(EXT_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") +set(EXT_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") diff --git a/scripts/cmake/timing_adapter/ta_config_u85_high_end.cmake b/scripts/cmake/timing_adapter/ta_config_u85_high_end.cmake new file mode 100644 index 0000000..98a9be0 --- /dev/null +++ b/scripts/cmake/timing_adapter/ta_config_u85_high_end.cmake @@ -0,0 +1,68 @@ +#---------------------------------------------------------------------------- +# SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its +# affiliates <open-source-office@arm.com> +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +#---------------------------------------------------------------------------- +# CMake description file for the Arm Ethos-U85 Timing Adapter settings (single +# NPU core with three, four or six AXIs). +#---------------------------------------------------------------------------- + +# The platform CMake infra should set the base register values for +# TA component to work. For Ethos-U85, we need at least three base addresses. +if (NOT DEFINED TA_SRAM0_BASE OR NOT DEFINED TA_SRAM1_BASE OR NOT DEFINED TA_EXT0_BASE) + message(FATAL_ERROR "TA_SRAM0_BASE, TA_SRAM1_BASE and TA_EXT0_BASE need to be defined.") +endif () + +message(STATUS "using TA_SRAM0_BASE @ ${TA_SRAM0_BASE}; TA_SRAM1_BASE @ ${TA_SRAM1_BASE}; TA_EXT0_BASE @ ${TA_EXT0_BASE}.") + +# Timing adapter settings for SRAM +set(SRAM_MAXR "16" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") +set(SRAM_MAXW "16" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") +set(SRAM_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") +set(SRAM_RLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") +set(SRAM_WLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") +set(SRAM_PULSE_ON "3999" CACHE STRING "No. of cycles addresses let through (0-65535).") +set(SRAM_PULSE_OFF "1" CACHE STRING "No. of cycles addresses blocked (0-65535).") +set(SRAM_BWCAP "4000" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") +set(SRAM_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") +set(SRAM_PERFCNT "0" CACHE STRING "32-bit event counter") +set(SRAM_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; + Bit 1: 1=enable random AR reordering (0=default); + Bit 2: 1=enable random R reordering (0=default); + Bit 3: 1=enable random B reordering (0=default); + Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") +set(SRAM_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") +set(SRAM_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") + +# Timing adapter settings for EXT +set(EXT_MAXR "24" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") +set(EXT_MAXW "12" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") +set(EXT_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") +set(EXT_RLATENCY "500" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") +set(EXT_WLATENCY "250" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") +set(EXT_PULSE_ON "4000" CACHE STRING "No. of cycles addresses let through (0-65535).") +set(EXT_PULSE_OFF "1000" CACHE STRING "No. of cycles addresses blocked (0-65535).") +set(EXT_BWCAP "1172" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") +set(EXT_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") +set(EXT_PERFCNT "0" CACHE STRING "32-bit event counter") +set(EXT_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; + Bit 1: 1=enable random AR reordering (0=default); + Bit 2: 1=enable random R reordering (0=default); + Bit 3: 1=enable random B reordering (0=default); + Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") +set(EXT_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") +set(EXT_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") diff --git a/scripts/py/vela_configs.py b/scripts/py/vela_configs.py new file mode 100644 index 0000000..b4af9fd --- /dev/null +++ b/scripts/py/vela_configs.py @@ -0,0 +1,150 @@ +#!/usr/bin/env python3 +# SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +""" +Classes to represent NPU configurations for Vela +""" +import itertools +import typing +from dataclasses import dataclass + +# The internal SRAM size for Corstone-300 implementation on MPS3 specified by AN552 +# The internal SRAM size for Corstone-310 implementation on MPS3 specified by AN555 +# is 4MB, but we are content with the 2MB specified below. +MPS3_MAX_SRAM_SZ = 2 * 1024 * 1024 # 2 MiB (2 banks of 1 MiB each) + + +@dataclass(frozen=True) +class NpuConfig: + """ + Represents a Vela configuration for an NPU + """ + name_prefix: str + macs: int + processor_id: str + prefix_id: str + memory_mode: str + system_config: str + arena_cache_size: int = 0 + + @property + def config_name(self) -> str: + """ + Get the name of the configuration + + For example: "ethos-u55-128" would represent the Ethos-U55 NPU + with a 128 MAC configuration. + + :return: The NPU configuration name. + """ + return f"{self.name_prefix}-{self.macs}" + + @property + def config_id(self) -> str: + """ + Get the configuration id as a string + + For example: "Y256" would represent the Ethos-U65 NPU + with a 256 MAC configuration. + + :return: The NPU configuration id. + """ + return f"{self.prefix_id}{self.macs}" + + def overwrite_arena_cache_size(self, arena_cache_size): + """ + Get a new NPU configuration with the specified + arena cache size. + + By default, we use the `arena_cache_size` value in the + `default_vela.ini` configuration file. + + :param arena_cache_size: The new arena cache size value. + :return: A new NPU configuration with the new + arena cache size value. + """ + value = arena_cache_size + + if value == 0: + value = MPS3_MAX_SRAM_SZ if self.memory_mode == "Shared_Sram" else None + + return NpuConfig( + **{**self.__dict__, **{"arena_cache_size": value}} + ) + + +@dataclass(frozen=True) +class NpuConfigs: + """ + Represents a collection of NPU configurations. + """ + configs: typing.Dict[str, typing.Dict[int, NpuConfig]] + + @staticmethod + def create(*configs: NpuConfig): + """ + Create a new collection with the specified NPU configurations. + + :param configs: NPU configuration objects to add to the collection. + :return: A new collection of NPU configurations. + """ + _configs = {} + + # Internal data structure of nested dictionaries based on + # NPU name and MAC configuration, e.g.: + # _configs["ethos-u55"][128] + + for c in configs: + if c.name_prefix not in _configs: + _configs[c.name_prefix] = {} + _configs[c.name_prefix][c.macs] = c + return NpuConfigs(configs=_configs) + + def get(self, name_prefix: str, macs: typing.Union[int, str]) -> typing.Optional[NpuConfig]: + """ + Get an NPU configuration by name prefix and MAC configuration. + + :param name_prefix: The name prefix, e.g. "ethos-u55". + :param macs: The MAC configuration, e.g. 128. + :return: The matching NPU configuration, or None if no such configuration + exists in the collection. + """ + configs_for_name = self.configs.get(name_prefix) + if not configs_for_name: + return None + return configs_for_name.get(int(macs)) + + def get_by_name(self, name: str) -> typing.Optional[NpuConfig]: + """ + Get an NPU configuration by name. + + :param name: The NPU configuration name, e.g. "ethos-u55-128". + :return: The matching NPU configuration, or None if no such configuration + exists in the collection. + """ + name_prefix, macs = name.rsplit("-", 1) + return self.get(name_prefix, macs) + + @property + def names(self): + """ + Return a list of all NPU configuration names in the collection. + + :return: The list of NPU configuration names. + """ + return list(itertools.chain.from_iterable([ + [f"{c.name_prefix}-{c.macs}" for c in config.values()] + for config in self.configs.values() + ])) diff --git a/scripts/vela/default_vela.ini b/scripts/vela/default_vela.ini index 9d6baa7..5d4d48e 100644 --- a/scripts/vela/default_vela.ini +++ b/scripts/vela/default_vela.ini @@ -1,5 +1,5 @@ ; -; SPDX-FileCopyrightText: Copyright 2021 Arm Limited and/or its affiliates <open-source-office@arm.com> +; SPDX-FileCopyrightText: Copyright 2021, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); @@ -48,6 +48,71 @@ Dram_clock_scale=0.234375 Dram_burst_length=128 Dram_read_latency=500 Dram_write_latency=250 + +; SRAMx2 (16 GB/s) and DRAMx1 (3.75 GB/s) +[System_Config.Ethos_U85_SYS_DRAM_Low] +core_clock=500e6 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_ports_used=2 +Sram_burst_length=64 +Sram_read_latency=16 +Sram_write_latency=16 +Dram_clock_scale=0.46875 +Dram_ports_used=1 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + +; SRAMx2 (32 GB/s) and DRAM (12 GB/s) +[System_Config.Ethos_U85_SYS_DRAM_Mid_512] +core_clock=1e9 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_ports_used=2 +Sram_burst_length=64 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.75 +Dram_ports_used=1 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + +; SRAMx2 (32 GB/s) and DRAMx2 (24 GB/s) +[System_Config.Ethos_U85_SYS_DRAM_Mid_1024] +core_clock=1e9 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_ports_used=2 +Sram_burst_length=64 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.75 +Dram_ports_used=2 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + +; SRAMx4 (64 GB/s) and DRAMx2 (24 GB/s) +[System_Config.Ethos_U85_SYS_DRAM_High_2048] +core_clock=1e9 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_ports_used=4 +Sram_burst_length=64 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.75 +Dram_ports_used=2 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + ; ----------------------------------------------------------------------------- ; Memory Mode @@ -64,4 +129,4 @@ cache_mem_area=Axi0 const_mem_area=Axi1 arena_mem_area=Axi1 cache_mem_area=Axi0 -arena_cache_size=393216
\ No newline at end of file +arena_cache_size=393216 diff --git a/set_up_default_resources.py b/set_up_default_resources.py index 7ed9e97..b0df01a 100755 --- a/set_up_default_resources.py +++ b/set_up_default_resources.py @@ -36,29 +36,61 @@ from pathlib import Path from urllib.error import URLError from scripts.py.check_update_resources_downloaded import get_md5sum_for_file +from scripts.py.vela_configs import NpuConfigs, NpuConfig # Supported version of Python and Vela - -VELA_VERSION = "3.10.0" +VELA_VERSION = "f190b8c8" +INSTALL_VELA_FROM_SOURCE = True py3_version_minimum = (3, 10) +u85_macs_to_system_configs = { + 128: "Ethos_U85_SYS_DRAM_Low", + 256: "Ethos_U85_SYS_DRAM_Low", + 512: "Ethos_U85_SYS_DRAM_Mid_512", + 1024: "Ethos_U85_SYS_DRAM_Mid_1024", + 2048: "Ethos_U85_SYS_DRAM_High_2048", +} + # Valid NPU configurations: -valid_npu_config_names = [ - "ethos-u55-32", - "ethos-u55-64", - "ethos-u55-128", - "ethos-u55-256", - "ethos-u65-256", - "ethos-u65-512", -] +valid_npu_configs = NpuConfigs.create( + *( + NpuConfig( + name_prefix="ethos-u55", + macs=macs, + processor_id="U55", + prefix_id="H", + memory_mode="Shared_Sram", + system_config="Ethos_U55_High_End_Embedded", + ) for macs in (32, 64, 128, 256) + ), + *( + NpuConfig( + name_prefix="ethos-u65", + macs=macs, + processor_id="U65", + prefix_id="Y", + memory_mode="Dedicated_Sram", + system_config="Ethos_U65_High_End" + ) for macs in (256, 512) + ), + *( + NpuConfig( + name_prefix="ethos-u85", + macs=macs, + processor_id="U85", + prefix_id="Z", + memory_mode="Dedicated_Sram", + system_config=u85_macs_to_system_configs[macs] + ) for macs in (128, 256, 512, 1024, 2048) + ) +) # Default NPU configurations (these are always run when the models are optimised) -default_npu_config_names = [valid_npu_config_names[2], valid_npu_config_names[4]] - -# The internal SRAM size for Corstone-300 implementation on MPS3 specified by AN552 -# The internal SRAM size for Corstone-310 implementation on MPS3 specified by AN555 -# is 4MB, but we are content with the 2MB specified below. -MPS3_MAX_SRAM_SZ = 2 * 1024 * 1024 # 2 MiB (2 banks of 1 MiB each) +default_npu_configs = NpuConfigs.create( + valid_npu_configs.get("ethos-u55", 128), + valid_npu_configs.get("ethos-u65", 256), + valid_npu_configs.get("ethos-u85", 512), +) default_use_case_resources_path = (Path(__file__).parent.resolve() / 'scripts' / 'py' / 'use_case_resources.json') @@ -68,19 +100,6 @@ default_requirements_path = (Path(__file__).parent.resolve() @dataclass(frozen=True) -class NpuConfig: - """ - Represent an NPU configuration for Vela - """ - config_name: str - memory_mode: str - system_config: str - ethos_u_npu_id: str - ethos_u_config_id: str - arena_cache_size: str - - -@dataclass(frozen=True) class UseCaseResource: """ Represent a use case's resource @@ -127,8 +146,8 @@ class SetupArgs: use_case_names: typing.List[str] = () arena_cache_size: int = 0 check_clean_folder: bool = False - additional_requirements_file: Path = "" - use_case_resources_file: Path = "" + additional_requirements_file: typing.Optional[Path] = "" + use_case_resources_file: typing.Optional[Path] = "" def load_use_case_resources( @@ -207,43 +226,19 @@ def get_default_npu_config_from_name( Returns: ------- - NPUConfig: An NPU config named tuple populated with defaults for the given - config name + NpuConfig: An NpuConfig populated with defaults for the given config name """ - if config_name not in valid_npu_config_names: + npu_config = valid_npu_configs.get_by_name(config_name) + + if not npu_config: raise ValueError( f""" Invalid Ethos-U NPU configuration. - Select one from {valid_npu_config_names}. + Select one from {valid_npu_configs.names}. """ ) - strings_ids = ["ethos-u55-", "ethos-u65-"] - processor_ids = ["U55", "U65"] - prefix_ids = ["H", "Y"] - memory_modes = ["Shared_Sram", "Dedicated_Sram"] - system_configs = ["Ethos_U55_High_End_Embedded", "Ethos_U65_High_End"] - memory_modes_arena = { - # For shared SRAM memory mode, we use the MPS3 SRAM size by default. - "Shared_Sram": MPS3_MAX_SRAM_SZ if arena_cache_size <= 0 else arena_cache_size, - # For dedicated SRAM memory mode, we do not override the arena size. This is expected to - # be defined in the Vela configuration file instead. - "Dedicated_Sram": None if arena_cache_size <= 0 else arena_cache_size, - } - - for i, string_id in enumerate(strings_ids): - if config_name.startswith(string_id): - npu_config_id = config_name.replace(string_id, prefix_ids[i]) - return NpuConfig( - config_name=config_name, - memory_mode=memory_modes[i], - system_config=system_configs[i], - ethos_u_npu_id=processor_ids[i], - ethos_u_config_id=npu_config_id, - arena_cache_size=memory_modes_arena[memory_modes[i]], - ) - - return None + return npu_config.overwrite_arena_cache_size(arena_cache_size) def remove_tree_dir(dir_path: Path): @@ -414,7 +409,7 @@ def run_vela( # We want the name to include the configuration suffix. For example: vela_H128, # vela_Y512 etc. - new_suffix = "_vela_" + config.ethos_u_config_id + ".tflite" + new_suffix = "_vela_" + config.config_id + ".tflite" new_vela_optimised_model_path = model.parent / (model.stem + new_suffix) skip_optimisation = new_vela_optimised_model_path.is_file() @@ -585,7 +580,13 @@ def set_up_python_venv( call_command(command) # 1.4 Make sure to have all the main requirements - requirements = [f"ethos-u-vela=={VELA_VERSION}"] + if INSTALL_VELA_FROM_SOURCE: + requirements = [ + f"git+https://review.mlplatform.org/ml/ethos-u/ethos-u-vela.git@{VELA_VERSION}" + ] + else: + requirements = [f"ethos-u-vela=={VELA_VERSION}"] + command = f"{env_python} -m pip freeze" packages = call_command(command) for req in requirements: @@ -702,7 +703,7 @@ def set_up_resources(args: SetupArgs) -> Path: env_activate, args.arena_cache_size, npu_config_names=list( - set(default_npu_config_names + list(args.additional_npu_config_names)) + set(default_npu_configs.names + list(args.additional_npu_config_names)) ) ) @@ -728,7 +729,7 @@ if __name__ == "__main__": parser.add_argument( "--additional-ethos-u-config-name", help=f"""Additional (non-default) configurations for Vela: - {valid_npu_config_names}""", + {valid_npu_configs.names}""", default=[], action="append", ) diff --git a/source/hal/source/components/npu/CMakeLists.txt b/source/hal/source/components/npu/CMakeLists.txt index eebf235..9ccb9a4 100644 --- a/source/hal/source/components/npu/CMakeLists.txt +++ b/source/hal/source/components/npu/CMakeLists.txt @@ -17,7 +17,7 @@ #---------------------------------------------------------------------------- ######################################################### -# Ethos-U NPU initialization library # +# Arm Ethos-U NPU initialization library # ######################################################### cmake_minimum_required(VERSION 3.21.0) @@ -73,11 +73,20 @@ elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Shared_Sram) # Shared Sram can be used for Ethos-U55 and Ethos-U65 set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM") elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Dedicated_Sram) - # Dedicated Sram is used only for Ethos-U65 - if (ETHOS_U_NPU_ID STREQUAL U65) - list(APPEND ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM" "-DETHOS_U_NPU_CACHE_SIZE=${ETHOS_U_NPU_CACHE_SIZE}") + # Dedicated Sram is used only for Ethos-U65 and Ethos-U85 + if (ETHOS_U_NPU_ID STREQUAL U65 OR ETHOS_U_NPU_ID STREQUAL U85) + list( + APPEND + ETHOS_U_NPU_MEMORY_MODE_FLAG + "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM" + "-DETHOS_U_NPU_CACHE_SIZE=${ETHOS_U_NPU_CACHE_SIZE}" + ) else () - message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `dedicated_sram` can be used only for Ethos-U65.") + message( + FATAL_ERROR + "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. " + "`dedicated_sram` can be used only for Ethos-U65 or Ethos-U85." + ) endif () else () message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode ${ETHOS_U_NPU_MEMORY_MODE}") @@ -128,15 +137,20 @@ else() NPU_REGIONCFG_1=0) # AXI0=M0 for U55/U65 endif() -# Ethos-U55 supports a maximum burst length of 64 bytes while Ethos-U65 supports up to 128 bytes. +# Ethos-U55 supports a maximum burst length of 64 bytes, Ethos-U65 supports up to 128 bytes, +# and Ethos-U85 supports up to 256 bytes. # Although, this is system implementation dependent the platforms we build for should support the -# maximum burst length for both NPU configurations. +# maximum burst length for all NPU configurations. if (ETHOS_U_NPU_ID STREQUAL U65) target_compile_definitions(ethosu_core_driver PRIVATE AXI_LIMIT0_MAX_BEATS_BYTES=1 AXI_LIMIT1_MAX_BEATS_BYTES=1 AXI_LIMIT2_MAX_BEATS_BYTES=1 AXI_LIMIT3_MAX_BEATS_BYTES=1) # 0 = 64 byte burst & 1 = 128 byte burst +elseif (ETHOS_U_NPU_ID STREQUAL U85) + target_compile_definitions(ethosu_core_driver PRIVATE + AXI_LIMIT_SRAM_MAX_BEATS=2 + AXI_LIMIT_EXT_MAX_BEATS=2) # 0 = 64 byte burst, 1 = 128 byte burst, 2 = 256 byte burst endif() # Create static library diff --git a/source/hal/source/components/npu/ethosu_profiler.c b/source/hal/source/components/npu/ethosu_profiler.c index dea704c..77671a8 100644 --- a/source/hal/source/components/npu/ethosu_profiler.c +++ b/source/hal/source/components/npu/ethosu_profiler.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -79,6 +79,7 @@ void ethosu_pmu_init(void) /* Total counters = event counters + derived counters + total cycle count */ counters->num_total_counters = ETHOSU_PROFILER_NUM_COUNTERS; +#if defined(ETHOSU55) || defined(ETHOSU65) #if ETHOSU_PMU_NCOUNTERS >= 4 counters->npu_evt_counters[0].event_type = ETHOSU_PMU_NPU_ACTIVE; counters->npu_evt_counters[0].event_mask = ETHOSU_PMU_CNT1_Msk; @@ -102,6 +103,34 @@ void ethosu_pmu_init(void) #else /* ETHOSU_PMU_NCOUNTERS >= 4 */ #error "NPU PMU expects a minimum of 4 available event triggered counters!" #endif /* ETHOSU_PMU_NCOUNTERS >= 4 */ +#elif defined(ETHOSU85) +#if ETHOSU_PMU_NCOUNTERS >= 8 + counters->npu_evt_counters[0].event_type = ETHOSU_PMU_NPU_ACTIVE; + counters->npu_evt_counters[0].event_mask = ETHOSU_PMU_CNT1_Msk; + counters->npu_evt_counters[0].name = "NPU ACTIVE"; + counters->npu_evt_counters[0].unit = unit_cycles; + + counters->npu_evt_counters[1].event_type = ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED; + counters->npu_evt_counters[1].event_mask = ETHOSU_PMU_CNT2_Msk; + counters->npu_evt_counters[1].name = "NPU ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED"; + counters->npu_evt_counters[1].unit = unit_beats; + + counters->npu_evt_counters[2].event_type = ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN; + counters->npu_evt_counters[2].event_mask = ETHOSU_PMU_CNT3_Msk; + counters->npu_evt_counters[2].name = "NPU ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN"; + counters->npu_evt_counters[2].unit = unit_beats; + + counters->npu_evt_counters[3].event_type = ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED; + counters->npu_evt_counters[3].event_mask = ETHOSU_PMU_CNT4_Msk; + counters->npu_evt_counters[3].name = "NPU ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED"; + counters->npu_evt_counters[3].unit = unit_beats; + + counters->npu_evt_counters[4].event_type = ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN; + counters->npu_evt_counters[4].event_mask = ETHOSU_PMU_CNT5_Msk; + counters->npu_evt_counters[4].name = "NPU ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN"; + counters->npu_evt_counters[4].unit = unit_beats; +#endif /* ETHOSU_PMU_NCOUNTERS >= 8 */ +#endif /* defined(ETHOSU55) || defined(ETHOSU65) */ #if ETHOSU_DERIVED_NCOUNTERS >= 1 counters->npu_derived_counters[0].name = "NPU IDLE"; diff --git a/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template b/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template index a1a2251..d6cc79a 100644 --- a/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template +++ b/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2021 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2021, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,45 +20,52 @@ #ifndef TIMING_ADAPTER_SETTINGS_H #define TIMING_ADAPTER_SETTINGS_H -#cmakedefine TA0_BASE (@TA0_BASE@) -#cmakedefine TA1_BASE (@TA1_BASE@) +#cmakedefine TA_SRAM0_BASE (@TA_SRAM0_BASE@) +#cmakedefine TA_SRAM1_BASE (@TA_SRAM1_BASE@) +#cmakedefine TA_SRAM2_BASE (@TA_SRAM2_BASE@) +#cmakedefine TA_SRAM3_BASE (@TA_SRAM3_BASE@) +#cmakedefine TA_EXT0_BASE (@TA_EXT0_BASE@) +#cmakedefine TA_EXT1_BASE (@TA_EXT1_BASE@) -/* Timing adapter settings for AXI0 */ -#if defined(TA0_BASE) +/* Timing adapter settings for SRAM */ +#if defined(TA_SRAM0_BASE) \ + || defined(TA_SRAM1_BASE) \ + || defined(TA_SRAM2_BASE) \ + || defined(TA_SRAM3_BASE) -#define TA0_MAXR (@TA0_MAXR@) -#define TA0_MAXW (@TA0_MAXW@) -#define TA0_MAXRW (@TA0_MAXRW@) -#define TA0_RLATENCY (@TA0_RLATENCY@) -#define TA0_WLATENCY (@TA0_WLATENCY@) -#define TA0_PULSE_ON (@TA0_PULSE_ON@) -#define TA0_PULSE_OFF (@TA0_PULSE_OFF@) -#define TA0_BWCAP (@TA0_BWCAP@) -#define TA0_PERFCTRL (@TA0_PERFCTRL@) -#define TA0_PERFCNT (@TA0_PERFCNT@) -#define TA0_MODE (@TA0_MODE@) -#define TA0_HISTBIN (@TA0_HISTBIN@) -#define TA0_HISTCNT (@TA0_HISTCNT@) +#define SRAM_MAXR (@SRAM_MAXR@) +#define SRAM_MAXW (@SRAM_MAXW@) +#define SRAM_MAXRW (@SRAM_MAXRW@) +#define SRAM_RLATENCY (@SRAM_RLATENCY@) +#define SRAM_WLATENCY (@SRAM_WLATENCY@) +#define SRAM_PULSE_ON (@SRAM_PULSE_ON@) +#define SRAM_PULSE_OFF (@SRAM_PULSE_OFF@) +#define SRAM_BWCAP (@SRAM_BWCAP@) +#define SRAM_PERFCTRL (@SRAM_PERFCTRL@) +#define SRAM_PERFCNT (@SRAM_PERFCNT@) +#define SRAM_MODE (@SRAM_MODE@) +#define SRAM_HISTBIN (@SRAM_HISTBIN@) +#define SRAM_HISTCNT (@SRAM_HISTCNT@) -#endif /* defined(TA0_BASE) */ +#endif /* defined(TA_SRAM0_BASE) */ -/* Timing adapter settings for AXI1 */ -#if defined(TA1_BASE) +/* Timing adapter settings for EXT */ +#if defined(TA_EXT0_BASE) || defined(TA_EXT1_BASE) -#define TA1_MAXR (@TA1_MAXR@) -#define TA1_MAXW (@TA1_MAXW@) -#define TA1_MAXRW (@TA1_MAXRW@) -#define TA1_RLATENCY (@TA1_RLATENCY@) -#define TA1_WLATENCY (@TA1_WLATENCY@) -#define TA1_PULSE_ON (@TA1_PULSE_ON@) -#define TA1_PULSE_OFF (@TA1_PULSE_OFF@) -#define TA1_BWCAP (@TA1_BWCAP@) -#define TA1_PERFCTRL (@TA1_PERFCTRL@) -#define TA1_PERFCNT (@TA1_PERFCNT@) -#define TA1_MODE (@TA1_MODE@) -#define TA1_HISTBIN (@TA1_HISTBIN@) -#define TA1_HISTCNT (@TA1_HISTCNT@) +#define EXT_MAXR (@EXT_MAXR@) +#define EXT_MAXW (@EXT_MAXW@) +#define EXT_MAXRW (@EXT_MAXRW@) +#define EXT_RLATENCY (@EXT_RLATENCY@) +#define EXT_WLATENCY (@EXT_WLATENCY@) +#define EXT_PULSE_ON (@EXT_PULSE_ON@) +#define EXT_PULSE_OFF (@EXT_PULSE_OFF@) +#define EXT_BWCAP (@EXT_BWCAP@) +#define EXT_PERFCTRL (@EXT_PERFCTRL@) +#define EXT_PERFCNT (@EXT_PERFCNT@) +#define EXT_MODE (@EXT_MODE@) +#define EXT_HISTBIN (@EXT_HISTBIN@) +#define EXT_HISTCNT (@EXT_HISTCNT@) -#endif /* defined(TA1_BASE) */ +#endif /* defined(TA_EXT0_BASE) */ #endif /* TIMING_ADAPTER_SETTINGS_H */ diff --git a/source/hal/source/components/npu_ta/ethosu_ta_init.c b/source/hal/source/components/npu_ta/ethosu_ta_init.c index 1ef4ff5..fc2b905 100644 --- a/source/hal/source/components/npu_ta/ethosu_ta_init.c +++ b/source/hal/source/components/npu_ta/ethosu_ta_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,62 +22,103 @@ #include "timing_adapter.h" /* Arm Ethos-U timing adapter driver header */ #include "timing_adapter_settings.h" /* Arm Ethos-U timing adapter settings */ +static uint32_t init_ta(uintptr_t base_addr, + struct timing_adapter_settings * ta_s, + char * name, + uint8_t idx) { + struct timing_adapter ta; + + if (0 != ta_init(&ta, base_addr)) { + printf_err("TA_%s%" PRIx8 " initialisation failed\n", name, idx); + return 1; + } + + ta_set_all(&ta, ta_s); + info("Configured TA_%s%" PRIx8 "\t@0x%" PRIx32 "\n", name, idx, base_addr); + return 0; +} + +static uint32_t init_sram_ta(uintptr_t base_addr, uint8_t idx) { + struct timing_adapter_settings ta_s = { + .maxr = SRAM_MAXR, + .maxw = SRAM_MAXW, + .maxrw = SRAM_MAXRW, + .rlatency = SRAM_RLATENCY, + .wlatency = SRAM_WLATENCY, + .pulse_on = SRAM_PULSE_ON, + .pulse_off = SRAM_PULSE_OFF, + .bwcap = SRAM_BWCAP, + .perfctrl = SRAM_PERFCTRL, + .perfcnt = SRAM_PERFCNT, + .mode = SRAM_MODE, + .maxpending = 0, /* This is a read-only parameter */ + .histbin = SRAM_HISTBIN, + .histcnt = SRAM_HISTCNT + }; + + return init_ta(base_addr, &ta_s, "SRAM", idx); +} + + +static uint32_t init_ext_ta(uintptr_t base_addr, uint8_t idx) { + struct timing_adapter_settings ta_s = { + .maxr = EXT_MAXR, + .maxw = EXT_MAXW, + .maxrw = EXT_MAXRW, + .rlatency = EXT_RLATENCY, + .wlatency = EXT_WLATENCY, + .pulse_on = EXT_PULSE_ON, + .pulse_off = EXT_PULSE_OFF, + .bwcap = EXT_BWCAP, + .perfctrl = EXT_PERFCTRL, + .perfcnt = EXT_PERFCNT, + .mode = EXT_MODE, + .maxpending = 0, /* This is a read-only parameter */ + .histbin = EXT_HISTBIN, + .histcnt = EXT_HISTCNT + }; + + return init_ta(base_addr, &ta_s, "EXT", idx); +} + + int arm_ethosu_timing_adapter_init(void) { -#if defined(TA0_BASE) - struct timing_adapter ta_0; - struct timing_adapter_settings ta_0_settings = { - .maxr = TA0_MAXR, - .maxw = TA0_MAXW, - .maxrw = TA0_MAXRW, - .rlatency = TA0_RLATENCY, - .wlatency = TA0_WLATENCY, - .pulse_on = TA0_PULSE_ON, - .pulse_off = TA0_PULSE_OFF, - .bwcap = TA0_BWCAP, - .perfctrl = TA0_PERFCTRL, - .perfcnt = TA0_PERFCNT, - .mode = TA0_MODE, - .maxpending = 0, /* This is a read-only parameter */ - .histbin = TA0_HISTBIN, - .histcnt = TA0_HISTCNT}; - - if (0 != ta_init(&ta_0, TA0_BASE)) { - printf_err("TA0 initialisation failed\n"); +#if defined(TA_SRAM0_BASE) + if (0 != init_sram_ta(TA_SRAM0_BASE, 0)) { return 1; } +#endif /* defined (TA_SRAM0_BASE) */ - ta_set_all(&ta_0, &ta_0_settings); - info("Configured TA0@0x%" PRIx32 "\n", TA0_BASE); -#endif /* defined (TA0_BASE) */ - -#if defined(TA1_BASE) - struct timing_adapter ta_1; - struct timing_adapter_settings ta_1_settings = { - .maxr = TA1_MAXR, - .maxw = TA1_MAXW, - .maxrw = TA1_MAXRW, - .rlatency = TA1_RLATENCY, - .wlatency = TA1_WLATENCY, - .pulse_on = TA1_PULSE_ON, - .pulse_off = TA1_PULSE_OFF, - .bwcap = TA1_BWCAP, - .perfctrl = TA1_PERFCTRL, - .perfcnt = TA1_PERFCNT, - .mode = TA1_MODE, - .maxpending = 0, /* This is a read-only parameter */ - .histbin = TA1_HISTBIN, - .histcnt = TA1_HISTCNT}; - - if (0 != ta_init(&ta_1, TA1_BASE)) - { - printf_err("TA1 initialisation failed\n"); +#if defined(TA_SRAM1_BASE) + if (0 != init_sram_ta(TA_SRAM1_BASE, 1)) { return 1; } +#endif /* defined (TA_SRAM1_BASE) */ - ta_set_all(&ta_1, &ta_1_settings); - info("Configured TA1@0x%" PRIx32 "\n", TA1_BASE); -#endif /* defined (TA1_BASE) */ +#if defined(TA_SRAM2_BASE) + if (0 != init_sram_ta(TA_SRAM2_BASE, 2)) { + return 1; + } +#endif /* defined (TA_SRAM2_BASE) */ + +#if defined(TA_SRAM3_BASE) + if (0 != init_sram_ta(TA_SRAM3_BASE, 3)) { + return 1; + } +#endif /* defined (TA_SRAM3_BASE) */ + +#if defined(TA_EXT0_BASE) + if (0 != init_ext_ta(TA_EXT0_BASE, 0)) { + return 1; + } +#endif /* defined (TA_EXT0_BASE) */ + +#if defined(TA_EXT1_BASE) + if (0 != init_ext_ta(TA_EXT1_BASE, 1)) { + return 1; + } +#endif /* defined (TA_EXT1_BASE) */ return 0; } diff --git a/source/hal/source/components/platform_pmu/include/platform_pmu.h b/source/hal/source/components/platform_pmu/include/platform_pmu.h index 09006dd..8077d31 100644 --- a/source/hal/source/components/platform_pmu/include/platform_pmu.h +++ b/source/hal/source/components/platform_pmu/include/platform_pmu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,7 +24,7 @@ extern "C" { #include <stdint.h> #include <stdbool.h> -#define NUM_PMU_COUNTERS (10) /**< Maximum number of available counters. */ +#define NUM_PMU_COUNTERS (12) /**< Maximum number of available counters. */ /** * @brief Container for a single unit for a PMU counter. diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt index 4f77bdd..672cbcd 100644 --- a/source/hal/source/platform/mps3/CMakeLists.txt +++ b/source/hal/source/platform/mps3/CMakeLists.txt @@ -35,23 +35,59 @@ endif() if (TARGET_SUBSYSTEM STREQUAL sse-300) set(UART0_BASE "0x49303000" CACHE STRING "UART base address") set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate") - set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)") set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address") set(ETHOS_U_IRQN "56" CACHE STRING "Ethos-U55 Interrupt") set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enable") set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable") - if (ETHOS_U_SEC_ENABLED) - set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") - if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) - set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") - set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") + if (ETHOS_U_NPU_ID STREQUAL U85) + if(ETHOS_U_NPU_CONFIG_ID MATCHES "^[A-Z]([0-9]+$)") + set(ETHOSU_MACS ${CMAKE_MATCH_1}) + else() + message(FATAL_ERROR "Couldn't work out Ethos-U number of MACS from ${ETHOS_U_NPU_CONFIG_ID}") endif() + if (ETHOS_U_SEC_ENABLED) + set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA_SRAM0_BASE "0x58104000" CACHE STRING "Ethos-U NPU timing adapter SRAM0") + set(TA_SRAM1_BASE "0x58104200" CACHE STRING "Ethos-U NPU timing adapter SRAM1") + if(ETHOSU_MACS STREQUAL "2048") + set(TA_SRAM2_BASE "0x58104400" CACHE STRING "Ethos-U NPU timing adapter SRAM2") + set(TA_SRAM3_BASE "0x58104600" CACHE STRING "Ethos-U NPU timing adapter SRAM3") + endif() + set(TA_EXT0_BASE "0x58104800" CACHE STRING "Ethos-U NPU timing adapter EXT0") + if(ETHOSU_MACS STREQUAL "1024" OR ETHOSU_MACS STREQUAL "2048") + set(TA_EXT1_BASE "0x58104A00" CACHE STRING "Ethos-U NPU timing adapter EXT1") + endif() + endif() + else () + set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA_SRAM0_BASE "0x48104000" CACHE STRING "Ethos-U NPU timing adapter SRAM0") + set(TA_SRAM1_BASE "0x48104200" CACHE STRING "Ethos-U NPU timing adapter SRAM1") + if(ETHOSU_MACS STREQUAL "2048") + set(TA_SRAM2_BASE "0x48104400" CACHE STRING "Ethos-U NPU timing adapter SRAM2") + set(TA_SRAM3_BASE "0x48104600" CACHE STRING "Ethos-U NPU timing adapter SRAM3") + endif() + set(TA_EXT0_BASE "0x48104800" CACHE STRING "Ethos-U NPU timing adapter EXT0") + if(ETHOSU_MACS STREQUAL "1024" OR ETHOSU_MACS STREQUAL "2048") + set(TA_EXT1_BASE "0x48104A00" CACHE STRING "Ethos-U NPU timing adapter EXT1") + endif() + endif() + endif () else () - set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address") - if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) - set(TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU timing adapter 0") - set(TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU timing adapter 1") + if (ETHOS_U_SEC_ENABLED) + set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA_SRAM0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter SRAM0") + set(TA_EXT0_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter EXT0") + endif() + else () + set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA_SRAM0_BASE "0x48103000" CACHE STRING "Ethos-U NPU timing adapter SRAM0") + set(TA_EXT0_BASE "0x48103200" CACHE STRING "Ethos-U NPU timing adapter EXT0") + endif() endif() endif () endif() @@ -60,7 +96,6 @@ endif() if (TARGET_SUBSYSTEM STREQUAL sse-310) set(UART0_BASE "0x49303000" CACHE STRING "UART base address") set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate") - set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)") set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address") set(ETHOS_U_IRQN "16" CACHE STRING "Ethos-U55 Interrupt") diff --git a/source/hal/source/platform/simple/CMakeLists.txt b/source/hal/source/platform/simple/CMakeLists.txt index e8bc14e..cfaa887 100644 --- a/source/hal/source/platform/simple/CMakeLists.txt +++ b/source/hal/source/platform/simple/CMakeLists.txt @@ -1,5 +1,5 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,8 +40,8 @@ set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enabl set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable") if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) - set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") - set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") + set(TA_SRAM0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") + set(TA_EXT0_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") endif() # 2. Create static library |