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SHRAM is removed from performance reports, as the SHRAM numbers only
include LUT usage.
Change-Id: I5d92bb3be9c8e38dad26ac8ef97c84ecb0aff2fa
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Fixed issue in removal of reshapes
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Id6081de8d6b7b6815cc5e56881c20e075214c407
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Uses LUT for int8/uint8 based tanh/sigmoid.
Change-Id: Ib6ac5a5c958ab9a17e47f620b22c3e22d8d60321
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Added check for inf numbers for all scales.
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
Change-Id: I84fcae429be4869d8489f66bef26863c254104cd
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Updated supported operator checks for StridedSlice:
- allow negative indices in begin/end values
- added more checks on shapes
Change-Id: I3ac76bfa6b313f0e2250f0749f152fb0e3aa033c
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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If IFM/OFM is not 4d rescaling ops are added to ReLus with
different scaling.
Change-Id: I631d44fc8a51fb476b9f62ef90eda26eef3d35f3
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
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Attempts to use fast storage for feature maps used in between
cascaded passes.
This is only relevant for system configurations where feature maps
are by default not placed in SRAM, but there is SRAM for fast storage.
Change-Id: I207b7cf32cfcb5bea3e6b93c2da1161c4af5221d
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Change-Id: I750ec63a0e37b38feaf4cbdcc883fdbef92bccdf
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
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Fixed issue with checking if axis corresponds to C-dim
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I72d9fd2c9fca642b5ab326324a63111b01c5de98
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Assign different equivalence ids to weights with same values but
different compression, to ensure correct addressing.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I13aabad71520e4f4a78fb2d6a81740bdd4d1256c
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- Added check for non-constant weights in supported operators
- Added check ifm & ifm2 shapes
- Handle None tensors for CPU operators
- Handle missing attributes for Cast operator
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
Change-Id: I2f16d3d44d0c6da5237550b39273cdb9cc3c7607
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Fixed incorrect ofm shape for some of the intermediate mul
operations in softmax int8/uint8.
Change-Id: I82351c1eb6a66b93280752f4cc00e2d0744d33b2
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Added support to convert batched FC to conv.
This enables choosing a suitable block-size.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Idc49e4fb6d29c554f10a38ece7996a7b7795ffad
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- Use non local memory as the base sram usage for a subgraph
- Make avoid_for_spilling more generic for all mem configs
Change-Id: I99cd30fe6a8ba075d5a70dc2138aa0635afaadb3
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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Compiled the new TensorFlow 2.3 schema and added the new Operator
BatchMatMul to tflite_mapping.py.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: Ie62517bd56a6497820e4f1ef20326a4fd2ca89b0
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Added logic for not using 40bit ACC for softmax int16.
Change-Id: I02b376040e19b48e8aaa65d48ffc7c47a0b9b187
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Added a static class TensorAddressMap that stores all Tensor addresses
based on their equivalence_id. Made the "address" field into a property
which getter and setter looks up/sets the tensor's address in
TensorAddressMap.
This makes the references to cpu_tensor/npu_tensor obsolete and they
have been removed.
Addition to scheduler: avoid SRAM spilling if an op has consumers in
other subgraphs.
Minor rework in LUTState; it will now assign a unique equivalence_id to
the SHRAM lut tensor to avoid issues with addressing. The equivalent
checks in LUTState now compares the values of the LUT instead of the the
equivalence_id.
Updated LUT unit tests accordingly.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I41de5a8a4e5f07b77d6544d8d4034b754993e503
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Allocate live ranges with longer life time first.
On average this gives better memory usage.
Change-Id: Id89e9e36a944169a2f10ce7f6e869397ef0abaf0
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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A Split operation with num_splits=1 is essentially
a NOP. This commit adds a graph optimisation function
which replaces said Split ops with an Identity op for
later pruning.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I0b0c535f214f54ee4c255662a18c37543bdc6d64
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Improved unit test coverage of fp_math.py
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I883fd984a1bfa67102826a400380e41a363fc59d
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- Only insert DMA op when IFM is for broadcasting and can't fit into
SHRAM
Change-Id: I3a7137bbc6311ce247353f04b7ab29e1bcbfe1f3
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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In the event we have a relu op with different input and output scales,
we need to fuse it with a nop avgpool.
Also refactor the existing avgpool nop code to a common function.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: Iedf4513e7595ee4ee1777ba0b1eb38a8df8aed5e
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Addded functionality for removing reshape OPs,
that enclose an Elementwize OP with only one non-constant
Tensor.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Idaac50cfbd732e2667668be2baa059673236cc56
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Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
Change-Id: I49c8d283eaa8d44839b94aaf4e90ec35365dc13f
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- Fixed SHRAM allocation for 8 and 16-bit elementwise ops
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I909a86d76e4ee6eab612aae827038b82703f28dc
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We have a number of sets for grouping specific ops together but arent
used that much in code. This updates the file to better utilise these
sets.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I719212671f8bdebc32576278f703549f0937ff65
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Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I3c3ed73a6db39615ddf5987dc5696b6b09682be0
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Allows fusing of LUT with a preceding operator regardless of
input/output scale.
Change-Id: Ia378adbb3fe61d71299feb085f7313377e0efa39
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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If a tflite file with no ops but just the input/output tensor is given,
vela wrote an empty optimised tflite file with no tensors given.
This fixes that by allowing all placeholder tensors to also be
serialised on write.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: If79817100869e712a75264889f401e38de0b1e7a
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Added batching to softmax by reshaping the input.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I0b516f9bf2410fb86372b229beba4a7280c498cc
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Removed CLI-option permanent-storage
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I03e03205a183bd538292a73a07b095546fa3d95a
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For SplitV sizesplit can contain one -1 indicating that
dimension is to be inferred.
Support added to handle this.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ib9fc8dd2ee1749e81a978d85f2d4a016698bb441
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Added the CLI option. Only applies to CPU tensors. Added an
AllocationError which is raised when Allocation fails.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I89164dea3ac7b7add7bc40aec2ce8fe50600105d
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Fix int16 multiplier saturation to match the reference.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I4a9c859482f7deb3899f90c7e9eb40c255ee4c45
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Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I75aad9bf59ad76ee6a0c0feb4d7299b50d787fe8
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Split mapping to tensor
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ic143f3b4d37f6904edd8f119eff1d108f70b5026
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Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I857aeb7aeb34f4b8ea47e6ac954cead268335e32
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Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I04618fd0d29075e7d3f8f27a320129603f045163
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- Set ACC_FORAMT to 32-bit for pooling operations.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I69ebd08c2db4c5ec966ca13c872c9b0c8330bb6f
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- Fixed bias check to use quantised values.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I6d87439938b9b5aeec87814e5a30d59fd06d5748
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- Corrected the rounding mode for softmax
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: If136491c7668e85fba1e2c56c8cff11aa32db328
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Fixed a zero point issue for int32 ifm.
Change-Id: I9149cb24d5b030ea5216a028a113518e458a8d15
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Enables LUT for LeakyRelu with int8/uint8 even if input scale
is different from the output scale.
Fusing LUT with a previous operator for this situation
requires further work.
Change-Id: I9eddfe36f457e763d44eb3e05fbe240eac7cfec9
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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- Processing reshapes at the end of NPU subgraphs selected NHCWB16
tensor format before handing over to the CPU. This commit detects
end-of-subgraph during the reshape-consumers compatibility check
and chooses NHWC format instead.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ieefdbecdba1a6183d79d3ac4d2505503dbf321cb
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Allows int64 data type to be used as long as all values can be packed
into a int40 value.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I0e25ec482e3ea765a5fd00bcf7e212a9e65a1461
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Fixed serialisation of scalar ifm tensors with values larger than
byte sized.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I2714398db91b83f24e5271c1d5de1c0e8211f9ab
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Added checks for not using NHCWB16 for reduce_sum int32 which makes
int8/uint8 softmax work.
Also enabled softmax graph rewrite by default and fixed a saturation
problem.
Change-Id: Ic01bd9ece7e5c3edb2900b7915cc747efe9e5760
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I287c24725126c169afec779b921e43c3ab26f739
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- Setup ifm/ifm2 based on primary op's inputs
Change-Id: I727eab473165d7cc876b70fa8873fbc0c1480fb5
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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Updated kernel size check, width and height was swapped
and added weight sum check.
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
Change-Id: Idb18cf258ac19b3a0d71134dab5a117bcd778b59
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